Design Of Back-end Data Acquisition And Processing Module In TS-ADC System

With the development of 5G communication,radar detection technologies and so on,data acquisition system is also facing higher requirements in speed,bandwidth and accuracy.Photonic time stretch analog-to-digital converter(TS-ADC)uses time-stretch technology to broaden the high frequency signal in time domain through the characteristics of broadband,low jitter,anti-electromagnetic interference of photonics.It breaks through the performance bottleneck of traditional electronic ADC,and greatly improves the analog bandwidth and sampling rate of data acquisition system.However,it is difficult to avoid the optical carrier envelope distortion and group velocity dispersion phase shift distortion in the process of time stretching,which makes it difficult to be widely used.Based on the background,the photonic time stretching technology is studied from the perspective of system,and a suitable back-end module is designed for the photonic TS-ADC in this thesis,which has the functions of data acquisition and signal correction processing.The main contents of the thesis are as follows:1.The scheme design of TS-ADC system back-end module.The design of signal acquisition module aims at high-speed and high-resolution.A dual-channel 10 GSPS signal acquisition module is designed in this thesis.The design scheme of high-speed data acquisition,sampling clock and memory module are given.After that,the mathematical expression and error source of TS-ADC front-end signal is analyzed in this thesis.Finally,the overall scheme design of back-end module is given.2.The design of TS-ADC system back-end acquisition module.A dual-channel design,in which each channel uses two 5.4GSPS ADC to form a 10 GSPS TIADC system,is adopted in this thesis.The principle JESD204 B interface protocol and the link establishment process is analyzed in this thesis.And the sampling data receiving logic in line with JESD204 B protocol operation mechanism is designed.The deterministic delay for synchronization is analyzed and implemented in subclass 1.According to the characteristics of the output signal of the photonic time skretching front-end,the trigger memory pre-processing logic design is completed to save storage resources and bandwidth.3.The design of signal processing module in TS-ADC system.For the distortion of the signal caused by uneven optical pulse envelope,considering the mismatch between channels,the envelope elimination module is designed to eliminate it.For the phase deviation caused by group velocity dispersion,a multi-phase FFT/IFFT algorithm with parallel structure is designed.The signal is transformed into the frequency domain,and the phase correction factor is participated in calculation to correct phase distortion in phase domain,and then it is restored to time domain signal.Finally,the functions and modules involved in the thesis are tested through the hardware test platform.The analysis results show that each module can achieve the design goal.