Research And Implementation Of TIADC Nonlinear Mismatch Eror Calibration Sub-channel Reconstruction Technology Based On Memory Polynomial

Analog-to-Digital Converter(ADC)plays a key role in the field of digital signal processing and is used in many fields such as 5G communications,automotive electronics,and biomedicine.In recent years,with the continuous improvement of semiconductor process technology,the requirements for the speed and accuracy of analog-to-digital converters have become higher and higher,and the existing analogto-digital converters can achieve high speed and high precision at the same time.The introduction of the Time-Interleaved ADC(TIADC)enables the sampling rate to be doubled while maintaining the accuracy of the original ADC.However,due to manufacturing process and device reasons,each ADC has different physical and electrical characteristics,so that the TIADC system will produce offset mismatch error,gain mismatch error,sampling time mismatch error,and nonlinear mismatch error.These mismatch errors will seriously affect the performance of TIADC,so these mismatch errors need to be calibrated.At present,there are relatively mature calibration methods for offset mismatch error,gain mismatch error and sampling time mismatch error.However,the nonlinear mismatch error has only gradually attracted scholars' attention in recent years,and there are few existing calibration methods.Therefore,this paper will mainly study the nonlinear mismatch error of TIADC and propose corresponding calibration algorithms.This thesis first uses memory polynomials to mathematically model the nonlinear mismatch error of TIADC,and proposes a method of nonlinear mismatch error calibration with memory effect based on sub-channel reconstruction.Use the subchannel reconstruction method to reconstruct the nonlinear mismatch error,and then subtract the error from the output to get the corrected output signal.The corrected output signal is fed back to the sub-channel reconstruction module to form a feedback loop to adaptively calibrate the coefficients of the nonlinear mismatch error estimated by the filtering and down-sampling least mean square method.And on this basis,the nonlinear mismatch error and the sampling time mismatch error are jointly corrected.Compared with other methods,the method proposed in this paper is suitable for TIADC with any number of channels,and can calibrate the non-linear mismatch error with memory effect.The sub-channel reconstruction structure does not require any test signals and modulation signals,and the entire calibration system works at a lower frequency,which greatly reduces the difficulty of hardware implementation,computational complexity and system power consumption.Then based on this mathematical model,a system model of the calibration algorithm was built using MATLAB software for simulation verification.Finally,based on the system model,the Verilog hardware description language is used to design the joint calibration method of the non-linear mismatch error and sampling time mismatch error of the 4-channel 14-bits TIADC,and the hardware implementation and verification are carried out using the FPGA development board.Experimental results show that the Spurious-Free Dynamic Range(SFDR)of the TIADC system has been increased from 49.09 d B before calibration to 76.86 dB.