The Design And Implementation Of High Speed Acquisition Module Based On JESD204B Protocol

In order to meet the more and more popular broadband sampling demand,the sampling rate of ADC is also rising constantly,at the same time,in order to meet the various dynamic range requirements of electronic systems,its resolution is rising too,thus bring Increasing data transfer rates between sampling and logic processing devices make conventional interface technologies(CMOS and LVDS)unable to meet the data transfer requirements of data converters and logic devices.The JESD204 B is a new interface standard between high-speed converter-to-logic processing devices that provides a high-performance,low-power,and flexible configuration interface solution.As the speed and resolution of the converter continue to increase,more data converters will select the JESD204 B interface as the data output interface.In this paper,a high-speed broadband acquisition module is designed for a broadband integrated system.The module mainly completes high-speed data acquisition and completes digital signal preprocessing.The main technologies involved are JESD20 B transmission technology between ADC chip and FPGA chip and multi-channel digital downconversion technology.In this paper,the JESD204 B interface protocol is analyzed in detail,and then the general scheme of the high-speed acquisition module is designed according to the design requirements.Then,the digital down-conversion and JESD204 B interface are designed.Finally,the design is tested.The JESD204 B interface transmission performance and multi-channel digital down conversion performance is verified by the test.The number of JESD204 B transmission links is 4,the single channel transmission rate is 4Gbps,the effective transmission rate of the link is 11.2Gbps,Through the actual data acquisition,its working parameters is meeting the design requirements.The multi-channel digital down-conversion section implements two 3-channel digital downconverter,which combine high-speed acquisition data of 400 MHz sampling rates into 3 baseband data channels with 10 MSPS,20MSPS and 40 MSPS data rates.Through the actual test,the digital down-converter operating parameters is meeting the design requirements.