Design And Hardware Realization Of Digital Down-Conversion Of Wideband Signal

With the continuous evolution of information technology,software defined radio(SDR)technology is considered to be the third revolution in the communications field after the transformation from analog communications to digital communications,from fixed communications to mobile communications,and from hardware to software.A new revolution of transformation.The application of software radio technology both in military and civilian fields has attracted more and more attention,and the digital down-conversion technology studied in this paper is one of the core technologies of software radio.The designed digital down-conversion module is connected to the digital channelization module.Suppose that when the signal has completed carrier frequency estimation and bandwidth estimation,first mix the channelized output signal to move the spectrum to the baseband.After that,different multiples of decimation are performed according to different bandwidths,and the maximum 512 times decimation can be achieved,effectively reducing the data rate for subsequent digital signal processing.In this paper,a detailed theoretical and algorithmic analysis of the digital down-conversion module in the receiver is carried out.According to the specific needs of the project,the main modules of digital down-conversion designed include five main modules: numerical control oscillation module,integrating comb filter bank,half-band decimation filter bank,FIR filter bank and digital automatic gain control.In the structure of the thesis,the above modules are analyzed separately at each stage of the research,and the principles of each part,the realization of the structure and the simulation effect are analyzed separately.The structure of the thesis starts from the basic theory of digital down-conversion,and analyzes it from shallow to deep in theory.It is modeled through the MATLAB simulation platform to determine that the algorithm used in the design is correct.After obtaining the correct module verification results,use the Verilog HDL hardware description language to perform FPGA hardware implementation and simulation analysis for each module,and compare the simulation results with the MATLAB platform simulation results to ensure the accuracy of the hardware implementation.In the specific implementation and simulation process,first through the ISE14.7 hardware platform,considering the module occupancy resources,an efficient structure design is adopted.Under the condition that real-time signal processing can be met,the overall multiplier usage of the digital down-conversion module is relatively better.Excellent level.Then through Model Sim for joint simulation verification to verify the hardware design from the timing.Finally,the framework diagrams of the overall design of the installation of the various modules of the design are integrated to realize an overall digital down-conversion module,which is burned in the Kintex-7XC7K325 T chip of Xilinx,and the hardware is tested to verify the correctness of the design.Digital down-conversion is the key to real-time signal processing and provides a technical solution for parallel signal processing in software radio.This paper is based on the background of software radio SDR to complete the design and hardware implementation of digital down-conversion of broadband signals,which is different from the implementation of dedicated digital signal processing chips.This scheme has good flexibility and adaptability,and has important engineering significance.