Research On Algorithms Of Artitrary Fractional Sampling Rate Conversion Based On Wideband Digital Receiver And Implementation Of Technology Based On FPGA

In order to satisfy the various communication protocol standards, processing speed and storage requirements, spawned many different sampling frequency. Although the current sampling rate conversion algorithm can solve the integer times of the factor of sampling rate conversion and arbitrary fractional sampling-rate conversion when the numerator and denominator are small, in the decimal factor of sampling rate conversion, it becomes bottleneck. Therefor, we study the arbitrary fractional sampling-rate conversion system around wide-band digital receiver. the main contents of this paper are organized as follows:First, we introduce the two important basic concepts in modern digital processing:the basic concepts of decimation and interpolation, and their effect on the signal spectrum. Then discuss the implementation of filter of interpolation and decimation and the applications of the combination of them. Then the specialities of polyphase structure filter is analyzed. In addition, we introduced several frequently-used digital filter, such as CIC filter and HB filter, and then analyzed its applicable occasions.Secondly, we study the previous fractional sampling-rate conversion algorithm in depth, getting two methods for realizing it:One is transforming the original digital signal into analog signal by D/A converter, the other is realizing it in the numeric-field absolutely. This paper provides the equation of interpolation filter via the second method. Then studied the characteristic of the Farrow structure and transposed Farrow structure, and finished the simulation.Considering the shortage of the single stage conversion system, this paper proposed an improved implementation scheme-the combination of the 3rd order Lagrange based on Farrow structure and integer decimation based on polynomial structure and completed the simulation. The simulation results shows that the disadvantage of this kind of program requires more hardware resources and design complexity and so on.Thirdly, this paper put forwards an efficient real-time sampling rate conversion method, and realizing it in the FPGA. The whole fractional sampling-rate conversion system which includes first stage FIR, second stage FIR, serial-to-parallel conversion circuit and the application operating system is firstly described and implemented using Verilog under the help of IDE of Xilinx company-ISE. The first stage is the core of this paper, mainly reflects the characteristics of any fractional multiplier. The second stage is a HB FIR filter, using multi-phase structure completed. And then, the behavioral level simulation is conducted using ModelSim simulation tools. After ensuring that the system functions correctly, we download it to the XC7K325T chip of Kintex-7 series made by Xilinx company for system verification.In addition, the compilation of the control interface program by PC is used for accessing the data of DDR3 at a high speed via PCIe. Then FFT processing makes use of the obtained data via Matlab for analyzing the system performance by observing the spectrum. And then optimizing its time consumption and space consumption. After the result tested by the system shows that, the fractional sampling-rate conversion system compared with polynomial interpolation algorithm, it not only achieves arbitrary fractional decimation well, but also good performance of anti-aliasing, requiring less than 1000 multipliers and adders, real-time, reducing to the level of a few hundred nanoseconds and run very fast and so on.Last but not least, we make a summary of this thesis and make a future research prospect.