Research On The The Technique Of Wideband Digital Down-Conversion Based On FPGA

Higher bandwith,higher precision,higher flexibility and more advanced anti-jam capability are required for modern radar.The mixer in conventional radar receiver is usually implemented with analog circuits,with A/D converter placed at intermediate-frequency(IF),which caused the problem,that the more analog devices are used,the poor performance and flexibility are provided to radar systems.Software Defiend Radio(SDR)emerged as the times require.In terms of SDR receiver,A/D is placed much closer to antenna.As is called the all-digital receiver,more signal processing components implementd by analog devices are replaced with the counterparts of digital devices,including quadrature demoduler and filters.New problems come along with the advantages of all-digtal receiver.With the demands of higher bandwith,higher sampling rate is required.Polyphase techniques and channelization method make high speed sampling become pratical.However,the mismanches between DSP and A/D make wideband Digital Down Converter(DDC)a research hotspot.The work of this thesis lies in the implemention of wideband DDC based on FPGA.The target signal is an LFM siginal with 120 MHz bandwith,2000 ns pulse width,400 MHZ IF and is sampled by a 14-bit,1.2GSPS ADC.To gain more than 50 dB out-of-band rejection and more flexibility,a reconfigurable wideband DDC is proposed,which consists of a parallel-NCO and 2-level cascaded FIR filter.In contrast,an alternative solution based on Xilinx IP Core is realized in this paper.It turns that the solution proposed by this paper can realize the DDC function with less comsuption.The main work of this thesis includes following four parts:First,an improved CORDIC arithmetic is proposed with logic reducement by 30%.Moreover,based on this improved CORDIC arithmetic,this article proposed a parallel NCO design which can serve as the mixer in wideband DDC.The second part is the design of FIR filter.2-level cascaded FIR filter is proposed to reduce the comsuption of logic resources on the premise of 50 d B out-of-band rejection.The 32-order,4-phase FIR filter is allocated in the first level,and what follows is a 47-order FIR filter with symmetric coefficient.On the other,a pipelined high-width adder is proposed to reduce the logic delay in the carry chain,and then this method is applied in the constant multiplier and adder tree in polyphase FIR filter.After the design,the papper complete the simulation of the system.LFM signal with IF 400 MHz and 120 MHz bandwith is simulated with 1.2GHz sampling rate in Matlab and serves as the input of DDC in Modelsim.The result is checked with spectrum analyzing in Matlab and the output waveform in Modelsim.In the end,to compare the logic resource consumption,this paper realize the same structure with Xilinx IP Core and compare the logic resource consumption of two design methods based on the same device.The result shows that the method proposed by this paper will consume fewer logic resources and no DSP Slices or Block RAMs,which make it a more universal IP which can implemented on different platform.