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Research And FPGA Implementation Of Ultra-wideband Receiver Based On Polyphase Filtering

Posted on:2011-03-16Degree:MasterType:Thesis
Country:ChinaCandidate:J J JiangFull Text:PDF
GTID:2178330338976222Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
The continuous developments of modern radar technology and the consequent more complicated electromagnetic environment have made it crucial to design wideband, digital, multifunctional software electronic reconnaissance receiver. Digital channelized receiver is an EW receiver that provides wideband frequency coverage, high sensitivity and dynamic range, high intercept probability and simultaneous signal detection and fine frequency resolution. In this dissertation, a structure based on polyphase decomposition is introduced, and how to detect signal and get PDW under the conditions of certain signal to noise rate when adopting the data output of the ADC is mainly discussed.First of all, one of the efficient architecture of digital channelized receiver based on polyphase filters is built in comparison with the basic architecture. The characteristics of polyphase filters are analyzed and the rabbit ear effect is preferably restrained as well. In order to have continuous coverage across of the IBW, adjacent channel responses are overlapped. The computer simulations experiments were done, and then the performances were analyzed deeply.Secondly, two kinds of signal detection and frequency measurement methods are discussed. Then one simple method based on amplitude comparison and Rife method is proposed. The false outputs can be eliminated and frequency-measurement accuracy can be highly improved by using this operation.Finally, a realization of channelized receivers based on poplyphase filtering on one FPGA chip is given in this paper. This design covers 1GHz bandwidth .This method resolves the contradiction between the high-speed ADC and low-speed digital signal processor (FPGA). The design can deal with both real-time signals and we introduce how to get the TOA, PW and IF based on Xilinx XC4VSX55. This method refers to performance on FPGA,and the system is simple, high speed and precision.
Keywords/Search Tags:digital channelized receiver, polyphase filter, parameter estimation, field programmable gate array (FPGA), fast Fourier transform (FFT)
PDF Full Text Request
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