With Rapid Capture And Large Capacity Storage Function Of High Speed Data Acquisition Module Design

With the development of electronic technology especially the integration-size increase and frequency improvement, engineers are setting higher expectation to electronic-measuring instruments, requesting higher sampling rate and storage capacity as well as better ability to capture waveform.Based on detailed analysis and design of the three key indexes including sampling rate, storage depth and capture rate, the author tries to improve them on the existing equipment and technology basis, making the achievement replicable and valuable for performance enhancement.Cooperating with a private enterprise, we defined two indexes including1GSPS highest sampling rate and16M storage depth to guarantee reliability and volume production, which satisfied equipment inspection demand in most situations.1、After the theoretical validation of data acquisition, processing and mass-storage plan, a double feature FPGA+DSP core control framework system was selected with two pieces of FPGA coordinately completing DSP instructions and assisting the front-end single ADC and back-end large-capacity memory chips, constituting the final overall structure of the system.2、In the high speed sampling module, we selected the single-chip scheme from the impedance matching and peripheral circuit perspective after analyzing several ones and chose the device, introducing synchronous data receiving and processing and back-end cache design after1GSPS high-speed sampling according to the data flow as well as the sample and the peak.3、In the mass storage module, controlling plan based on IPcore was selected in order to improve reliability, shorten research and development period and made it portable. Starting with the DDR2SDRAM visit principle, this paper introduced the function implementation of the internal controller and confirmed the clock management according to the input and output data, and then introduced the data flow trend, the cache realization, the clock, the addressing model and the particular pre-trigger structure.4、In the module of increasing capture rate, the time shown in traditional digital oscilloscopes was far more than the actual sampling time because of the signal regulation, storage and processing, which restricted the increase of capture rate. Based on the theoretical study of the relationship between capture rate and dead time, the author put forward a parallel-processing structure, setting a parallel processing module in FPGA to take place of DSP in waveform storing and mapping, which helped to improve the capture rate.