Design Of DPA-Resistant Power-Flattening Standard Cells

As the most representative,simplest and most efficient attack method in the sidechannel attack,Differential Power Analysis(DPA)is widely used in the field of cryptographic chip cracking.To resist the power attack and improve the security of the cryptographic chip,an independent and universal protection method is to protect the logic circuit at the bottom cell level.Based on the analysis of the power consumption characteristics of CMOS circuits and the implementation process of the DPA attack,this paper designs the DPA-resistant power-flattening standard cells to hide the correlation between the power consumption and the data.First of all,this paper summarize the characteristics of the existing dualrail pre-charge logics and propose a kind of Node Balanced Differential Logic(NBDL)based on the advantages of different dual-rail pre-charge logics.This logic structure takes into account the charging situation of all internal capacitor nodes during the evaluation phase and can achieve better power consumption flattening effect with less layout area.Secondly,this paper analyze the impact of power consumption delay on DPA attack,and study the sensitivity of different kinds of cells to DPA attack from the perspective of power consumption delay of the cell,and conclude that the sequential logic cell is more sensitive to DPA attack.Then a Three-phase Single-rail Pulse Register(TSPR)is proposed based on the three-phase operation mode.This structure ensures that each node in the register experiences a charge and discharge operation,so the register has a constant energy consumption for all processed data.Finally,to verify the protective effect of the designed cell,two logic structures are used to implement the simplified model circuit of AES.The simulation test results show that the NED index of each cell of NBDL is lower than 10%,and the NED index of TSPR is lower than 1%.In terms of the DPA-resistant performance of the simplified model circuit,the circuit implement with NBDL can reduce the correlation between the correct key and power consumption to 0.22 and the circuit implement with NBDL can reduce it to 0.1,which effectively improves the protection performance of the circuit.