Research On Circuit-level Design Against Power Analysis Attack For Cryptographic Chip

Cryptographic chip plays an important role in the information system. It is always the key of security control or the root of trust. Traditionally, the security of cryptographic chip depends on the mathematic complexity of the cryptographic algorithms, the authentication mode and the secure protocol. However, the security of cryptosystem rests on the most frangible component in the system. That means even if the cryptographic algorithm is secure theoretically, it may still be insecure due to improper physical implementation. Side-channel attacks and physical attacks are effective attacks against the cryptographic chip.Power analysis attack is a typical Side-channel attack method. It reveals the private keys by analyzing on the power consumption information leaked from cryptographic chips. Compared with traditional cryptanalysis, power analysis attack has less key search space and better analytical performance. Moreover, if combined with physical attacks or other Side-channel attacks, the efficiency of power analysis attack can be greatly improved.A successful power analysis attack depends on three main factors: First, the power consumption of cryptographic chip and its internal data have a certain correlation, this is the basis of power analysis attack; second, the attackers can accurately select the right power samples to validate this correlation, this is the premise of power analysis attack; third, the attacker's knowing about the implementing details of cryptographic algorithm, this determines the effectiveness power analysis attack. The target of this thesis is the power analysis resistance of cryptographic chip. By carefully analyzing the mechanism of circuit power and the theoretical foundation of power analysis attack, the research mainly focuses on the power analysis resistant circuit design and implementation technology. The contents include: eliminating the correlation between power consumption and internal data; increasing the difficulty to implement correlation validation; preventing the attackers to reveal implementation details of cryptographic algorithm.The innovations of this thesis are as follows:1. Proposing a noval dual rail pre-charge logic LBDL. At first, this thesis analyzed how the transition probability and transition time of logic cells influence the circuit power consumption, demonstrated the mechanism of the correlation between power consumption and internal data, as well as the security vulnerability in existing power analysis resistant logic. Based on the results of theoretical analysis, a novel power analysis resistant logic, LBDL, is proposed. It can completely achieve the constant characteristic of power consumption by eliminating early propagation effect. Compared with the typical power analysis resistant logic, the LBDL has similar performance, area and power consumption overhead, however, the power analysis resistant ability is improved several times.2. Proposing the implementation technology of dual rail pre-charge logic based circuit design. Based on the idea of standard cell replacement, this thesis proposed a complete dual rail pre-charge logic circuit design method. This design method can be incorporated by the common semi-custom design flow and utilize the current commercially available EDA tools to a large degree. Moreover, the static timing analysis problem in the early stage of the design flow and the balancing capacitance requirement of dual rail signals in routing phase are properly solved. Experiments show that the proposed method can effectively applied in circuit design. And the power analysis resistant ability of circuit can be greatly improved while the complexity of circuit design remains low.3. Proposing a novel power analysis resistant technology based on signal transition time randomization. As differential power analysis attack needs to align the power consumption samples according to the switching time of target signals, this thesis proposed a method to randomize the switching time of registers. In this case, the power analysis attack can be prevented. A power analysis platform based on FPGA is built and the proposed technology is compared with the regular implementation by experiment. The result confirms the power analysis resistant ability of the proposed technology.4. Proposing a technology to counteract both power analysis attack and layout reverse analyze. By layout reverse analyze, attackers can fully grasp the circuit details and improve the effectiveness of power analysis attack. This thesis proposes a power constant configurable logic, DRCL. On one hand, the uniform structure of DRCL can protect circuit details. On the other hand, the constant power consumption of DRCL can counteract power analysis attacks. Experimental results indicate that DRCL can eliminate most of the power leakage. Finally, a DRCL based FPGA is implemented, including the configurable routing structures, clock distribution tree and configuration structures.