Design Of ∑-△ Audio ADC Based On Oversampling Technology

Analog to Digital Converters play an important role in an ever-increasing digital world.∑-△ADC mainly Consist by the∑-△modulator and digital decimation filter,based on oversampling and noise shaping techniques,∑-△modulator pushes most of the noise energy to high frequencies out of the signal baseband,then the noise energy is filtered by the subsequent decimation filter,thereby gaining high SNR and resolution.∑-△ADC which takes advantage of the merits of modern VLSI techniques such as high speed,high level of the integrated,low power consumption,and is less sensitive to analog circuit non-idealities than Nyquist ADC,have been applied in high resolution requirement occasion.In this thesis,adopting the Top-Down design method,form the spec, the pin's function,system design,model design(circuit design/register transfer level code),the simulation,the layout,to the chip's test,and complete the 16 bits audio∑-△ADC design.The resolution and bandwidth of the∑-△ADC is determined by modulation, also the modulator is the key party of the∑-△ADC.The principle of the∑-△ADC are discussed firstly,then the basic theory and architecture of the∑-△modulator is introduced in detail,and give out how to design the modulator like as there parameters.In order to meet the high resolution and other performance requirement,three stage single loop fully differential switched capacitor architecture with three bits quantizer and 128 OSR is adopted in this system design.Then give out detail of the key circuits of the modulator and simulation result, such as sampling switch,Operational amplifiers,CMFB,two-phase non-overlapping clock generator circuits,bandgap reference,comparator, quantizer and so on.The followed is how to design digital decimation filter,like CIC filter,halfband filter,FIR filter and so on,also give out there specific implementation,the corresponding simulation results and synthesis netlist.Finally,the back-end chip design is discussed, including Synthesis by Design Compiler,Place and Route by Astro,STA by Prime Time,Post simulation by NC Simulator and chip test. This chip has been implemented in the TSMC 1P/5M 0.18um N-well CMOS standard silicon process.The chip area is only 1.20mm2,achieves to 16.9mW power consumption,98.6dB SNR,124.5dB DR and 0.0023dB THD for a 20KHz signal bandwidth with 1.8V digital supply,3.3V analog supply, 5.6448MHz frequency and 128 OSR,in a word,it's enough for 16 bits resolution,and achieve the desired design.