Study And Design Of ESD Protection In High-speed Integrated Circuit

The properties and functions of integrated circuits?ICs?have been improving due to the development of technology evolution and semiconductor industry.However,the decreasing in the size and increasing in the speed of ICs have made the electronic devices more sensitive to the electrostatic discharge?ESD?.ESD is a major reliability issue in the semiconductor industry.It is the single largest cause of all IC failures.ESD stress causes large electric fields and high current densities,resulting in breakdown of the oxide of CMOS and thermal damage.ESD protection in high-speed ICs becomes more challenging than others because it requests low parasitic capacitance,low leakage current and almost zero series resistance.To address this,dual-diode based ESD protection circuits,often named“rail-based”ESD protection circuits are widely implemented for radio-frequency?RF?,digital and high-speed interface ICs.In order to decrease the size and improve the reliability of the rail-based ESD protection circuits,the parasitic components?i.e.,the parasitic PNP bipolar transistor?in the circuits have been studied.Additionally,a new approach to improve the ESD properties of the rail-based ESD circuits was proposed in this paper.The ESD properties of the parasitic PNP bipolar transistor,which is formed by the high-side diode and the P substrate in the rail-based ESD protection circuit,is investigated,such as the triggering voltage(V_t1)and on-resistance(R_on),to prevent it from affecting the triggering of primary ESD cell and the normal operation of internal circuits.First,the method of ESD protection and the ESD design window were illustrated,and the operation of the common ESD protection devices and circuits were discussed.The layout of the high-side diode and the structure of the parasitic PNP bipolar transistor are also showed in this paper.The parasitic PNP was built and its parameters were adjusted to observe its ESD properties by the Silvaco technology computer aided design?TCAD?software next.The simulation results show that triggering voltage(V_t1)of the parasitic PNP varies with the geometry of the base region.The decreasing in the base region causes a considerable reduction of the V_t1.Additionally,some new structures of the parasitic PNP bipolar transistor were proposed,such as inserting N+region in P-well or N-well and adding high-doped region?i.e.,N-bridge and P-bridge?between the P-well and N-well,to modify its ESD properties.TCAD simulation results show that inserting a N+region in P well causes the snapback of the parasitic PNP,and the inset of the high-doped N bridge and P bridge leads to a reduction of the V_t1.Furthermore,the proposed parasitic PNP bipolar transistor with different structures was fabricated using the 65nm low-k logic/Mixed-Mode CMOS process and characterized with the ESDEMC transmission line pulse?TLP?system.The experimental results,which align well with the simulation results,present that the triggering voltage of parasitic PNP structures has strong dependence on the base region.