| Turbo codes are the most excellent error-correcting codes at present. The Turbo-code in 3Gpp TS25. 212 described by 3Gpp in WCDMA is researched in this paper. An algorithm model suitable for hardware implementation is built by expounding the SOVA algorithm in a method based on matrix. The extrinsic information memory including interleaver and deinterleaver is designed as a union memory, and the architecture of decoder is simplified. A Turbo decoder using SOVA is implemented in FPGA. The SOVA-based decoder occupies small hardware resources, which is meaningful to improve the performance of the communication devices in our country.In the Turbo decoder based on SOVA in this paper, the interleaver and deinterleaver is abstracted as an extrinsic information memory, and an elementary decoder is reused in iterative decoding, then a primary framework of compute-memory-control is built. An entity framework of SOVA-based Turbo decoder with clear structure and good extendability is founded. The decoder is implemented with FPGA. The decoder occupies small hardware resources--below 50% resources of a Spartan-3 FPGA. |
