A Design Of Embedded Block RAM For FPGA

Benefited from the development of technology and design methodology, more and more large-scale digital IC obtained better performance and greater integration density.As a major part of digital IC, FPGA even more so. The next generation of FPGA will use more advanced processes. More CPU or DSP modules will be embedded into FPGA.Structured ASIC will be another development direction of FPGA. Low-cost and nonvolatile device is getting increasingly popular.Compared to discrete memory devices, embedded block memory has the following features:?Compatible with the FPGA circuit, in line with the FPGA routing rules.? Highly programmable features: ports bit-width, memory depth and read-writemodeshould be programmable to meet the demands in different FPGA design occasions.? Because it is embedded into the FPGA chip, so the area constraint and powerconstraint is stricter.This paper discoursed an embedded block RAM(EBR), which applied in a FPGA chip. This type of EBR uses process as the same as FPGA for the reason of high integration density. The EBR has a wide variety of programmable features, such as configuration of single port RAM, dual port RAM, FIFO, ROM. Besides,different port bit-width is supported too, for example, 9bits width port, 4bits width port, 2bits width port, 1bit width port and double width. Read/Write mode contains normal mode, write through mode, read before write mode. Besides, programmable synchronous/asynchronous reset, programmable polarity clock is available. The physical area of the EBR is very small, there are 48 EBR blocks embedded in one FPGA chip.The topic of this paper comes from a FPGA project of Xian Intelligence Silicon Technology, Inc. Start with the design of memory bit-cell and delay-cell, then we studied the configuration of memory array. Based on the array configuration, we designed the X-decoder and Y-decoder circuit. At the end of this paper, we conducted EBR function verification and performance simulation. The result shows its function and performance meet the design requirements.