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High Speed And High Precision Digital-to-analog Converter (dac) Used In Gigabit Ethernet (1000base-t) Physical Layer Chip

Posted on:2009-04-05Degree:MasterType:Thesis
Country:ChinaCandidate:F HuangFull Text:PDF
GTID:2198360242483612Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
This paper is mainly focused on design of a high speed Digital-to-Analog Converter (DAC), which is used in Gigabit Ethernet (1000Base-T) Physical Layer Chip. According to the requirement of 802.3ab Standard, the transmitter includes a high speed Digital-to-Analog Converter (DAC). The specification of this DAC is 5-bit resolution, 8-bit accuracy, 125MHz sample rates and 4ns transition time, and the output of the DAC should include 17 levels.Glitch is the bottle-neck for the circuit design of high speed DAC. To meet the requirement of Gigabit Ethernet (1000Base-T) design, DAC of the transmitter should have an ability of 8-bit accuracy and 4ns transition time, so the circuit design of DAC should be improved to reduce the glitch. Basic theory, concepts and design method of DAC are illustrated in this paper. By comparison of the different architecture and decoder styles, Thermometer-Decoder Current Steering DAC is chosen as the appropriate implementation in the transmitter. Three key components of Thermometer-Decoder Current Steering DAC are Bandgap reference, current source arrary and latch arrary. Also the main source of the glitch is generated from these key components.In this design, a high PSRR bandgap is choosed to realize the current refence of DAC, it improves the system stablility and accuracy. This paper introduces an innovative structure for current source array: a cascaded architecture including eight current cells is adopted, where 8 current driver cells are controlled by consecutive 8 clock signals respectively, and the phase difference of any adjacent clock is 0.5ns. The gradational waveform is formed with turning on/off the clocks one by one when the output of DAC changes. A Low Pass Filter is used to smooth the staircase analog signals. This structure effectively reduces the glitch generated from the switching of current source array. Also an innovative latch circuit is introduced in this paper; it based on the positive feedback structure and can effectively reduce the glitch occurring at switching of the non-inphased controll signals for the current source.In this paper, the design had tape-out 0.13um process, and the design's performance is very good. Last, we summarize all reseach work of this paper and some advices are mentioned to optimize the transmitter in future research.
Keywords/Search Tags:Gigabit Ethernet, Transmitter, Test Mode, Digital-to-Analog Converter, Glitch
PDF Full Text Request
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