Optimization Of Parasitic Capacitance To Reduce The MOSFET Switching Loss

With the development of electronic technology in the field of high-frequency and high-power,power MOSFET is gradually enhancing its important status in semiconductor apparatus and is being widely applied in power converters as switch. With the increasing of the operating frequency ( > 200kHZ ),the energy loss caused by parasitic capacitance will affect the efficiency of power transforming in converters. Especially in the applications of high frequency power supply using MOSFET as main devices (the unit of frequency is MHZ),the energy loss caused by the switch process will badly affect its efficiency. So it is an important research in the field of the electronic technology to reduce the loss caused by the switching device and to improve the efficiency of high frequency power converters.This paper primarily focuses on the optimization of the MOSFET parasitic capacitance so as to reduce the switching loss and improve the efficiency of power transforming in converters using MOSFET as switch. After analyzing the switching characteristic of MOSFET,the object function of optimizing curve of the output capacitance Coss is confirmed according to the switching loss caused by outputcapacitance Coss,then the optimized curve of the output capacitance Coss is ascertained by applying Zoutendijk to seek the optimized value with constraint;The simulation of switching circuitry and DC-DC circuitry is tested at different frequency in PSPICE,then the least square method is adopted to fit simulation curves to calculate corresponding energy data. Finally,the optimized curve of the output capacitance Cms that can reduce the switching loss of the apparatus and improve the efficiency of power transforming in DC-DC circuitry is achieved according to the synthetical analysis of the simulation.