Design Technology Co-Optimization For Nanosheet Gate-All-Around Fets

As VLSI continues to follow Moore's Law,Nanosheet Gate-All-Around Field-Effect-Transistor(NSFET)is considered as the most promising alternative at the 3nm technology node.The Design Technology Co-Optimization(DTCO)is to optimize the DC/AC performance of devices through the Power-Performance-Area(PPA)characteristics of a specific circuit.DTCO has become the necessary method when exploring the core device of deep-nanometer process technology.In this work,3nm NSFET is simulated and optimized,and an improved DTCO is proposed for 3nm NSFET.Based on the process requirements and Contact Gate Pitch(CGP)constraints,the trade-off optimization of the structure parameters is realized.The main research contents and results are as follows:1.3nm NSFET modeling and simulation by TCAD are carried out combined with the actual process requirements.The strain engineering and structure such as overlap/underlap,low-k spacer,and nanosheet space(NSS)are optimized.The electrical characteristics of the optimized standard NSFET are excellent.The driving currents(I_ds)of NMOS and PMOS are 90.49?A and 88.07?A,the threshold voltages(V_th)are 0.124V and 0.137 V,and the sub-threshold swings(SS)are 65.5 mV/dec and73.7 mV/dec,and DIBL are 18 m V/V and 23 mV/V,respectively.2.An improved DTCO that combined the compact model of NSFET with the MEOL and BEOL parasitic model is proposed.The compact model of NSFET is extracted based on BSIM-CMG.For all the devices in this paper,the maximum RMS error of DC and capacitance characteristics are 1.34%and 2.70%,respectively.Subsequently,taking the inverter of the 3nm technology node as an example,the parasitic capacitance and resistance extraction method of the MEOL and BEOL is designed.The design process is proposed to combine the device model with the parasitic capacitance and resistance of the MEOL and BEOL to optimize the circuit,layout,and process collaboratively.3.Based on the proposed DTCO design process,the inverter,ring oscillator and NSFET are collaboratively optimized for the 3nm technology node.Considering the limitation of CGP and the influence of structure parameters on the process,the compromise of structure parameters is studied from the aspects of the NSFET electrical characteristics and the MEOL and BEOL parasitic characteristics.The circuit simulation analyzes the DC and transient characteristics of the inverter and the PPA characteristics of the ring oscillator.The proposed standard NSFET meets the scaling requirements from 5 nm to 3nm technology node,the area is reduced by 46%,the power consumption of RO is decreased by 42%,and the frequency of RO is increased by 20%.And there are also five NSFET structures satisfying the scaling requirement.The best one has achieved 46%reduction in area,48%reduction in power consumption,and 26%increase in speed.The research conclusions prove that device-level performance is not the only indicator in device optimization.It is necessary to combine the device electrical characteristics and the parasitic characteristics of MEOL and BEOL to realize collaborative optimization.And the requirements and constraints of the process also have a significant impact on circuit-level performance.The work has important guiding significance for the NSFET design and 3nm process development.