Research And Design On 200MS/s High Speed SAR ADC

Analog to Digital Converters(ADC),are the important components of communication system,Internet of Things system,and fiber-optic radio systems.ADCs with sampling rates in the 100-megahertz range are widely used in mobile communications,biomedicine,and automation systems,etc.As the front-end analogto-digital signal conversion processing module of the system,its performance is critical to subsequent digital signal processing.The successive approximation analog-to-digital converter(SAR ADC)has the characteristics of extremely low power consumption,small area and high accuracy,and is most suitable for future technology structures,so it can be used widely in cellular base stations,satellites and radar receivers,potable instruments and devices,and other fields.Thus,the research of high-speed and high-precision SAR ADC has practical significance.This paper surveys and summarizes the current research status of SAR ADC at home and abroad,analyzes several common structures of SAR ADCs,and finally,the system structure of the fully differential segmented capacitor is determined.Bootstrapped switch structure is designed to improve the linearity of the front-end sampling section,at the same time,improve the sampling accuracy and speed,adopting the redundant mosfet can ease the feed-through effect.An improved segmented capacitor array is adopted to reduce the total capacitance and effectively reduce the area.The DAC uses a partially monotonic switching scheme,the first two switching processes do not consume energy,which reduces the power consumption by about 50% compared with the traditional switching scheme.Adopting DAC parasitic capacitance correction technology based on variable capacitor array can improve the weight problem caused by parasitic capacitance DAC capacitor array,thereby improving the accuracy of SAR ADC,and simulation results show that the effective number of ADC after the correction is improved by 2 bits.The designe of a two-stage dynamic comparator improves the comparison speed and eliminates static power consumption,Monte Carlo simulation shows that the corrected offset voltage is only 0.3mV.The SAR control logic circuit obtains the comparison result and directly reflects it to the DAC switch,which improves the conversion speed of SAR.The serial output mode reduces the complexity of digital logic and reduces the chip area and power consumption.The entire circuit layout is completed using TSMC 40 nm CMOS process and layout area is195?m×140?m.Post-system simulation results show that: when sampling rate is 200MS/s,the input signal frequency is close to Nyquist frequency 95 MHz,SNDR is 51.2dB,SFDR is 54.6dB,and the power consumption is 9.3mW.