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Research On The Implementation Of FIR Digital Filter Based On FPGA

Posted on:2019-10-14Degree:MasterType:Thesis
Country:ChinaCandidate:L L LiuFull Text:PDF
GTID:2518306470494554Subject:Information and Communication Engineering
Abstract/Summary:PDF Full Text Request
In digital signal processing,FIR filter is applied more extensively than IIR filter because of the characteristics of stability and linear phase.While FPGA is the main implementation platform for signal processing,it is of great significance to study the implementation of FPGA-based FIR filters.This article describes the basic principles of the FIR filter in detail firstly.Then,after introducing three common design methods of FIR filter,several common structures of FIR filter are discussed.Because the performance of the filters is not only related to the design method,but also associated with the filter structure and hardware platform.Among the six structures,distributed structure which makes full use of the look-up table resources to replace multipliers has a great advantage.Therefore,the rest of this thesis mainly discusses the FPGA implementation of the distributed structure of FIR filters.For the size of the look-up table grows exponentially with the filter order,huge storage demand may result in excessive use of resources.In order to improve the performance of the distributed architecture,three optimization methods to reduce resource consumption are introduced.However,the different mapping methods of the distributed structure filter on the FPGA logic unit also affect the performance of the filter.Therefore,the following discussion focuses on the implementation of delay modules,addition modules,and memory modules on FPGAs in distributed architectures.Then,combined with the specific project requirements,an optimized distributed solution is proposed.Finally,on the XC7K325 T FPGA,we verify the performance of the above discussion and the optimized distributed scheme.Two important conclusions are obtained: For a 31-order filter,after the pre-add,the resources occupied are the least when the 16 effective filter coefficients are divided to three groups with one group of six coefficients,the others five coefficients each,;Moreover,the optimization scheme using this lookup table partitioning method reduces 44% of slice resources occupied by the distributed structure implemented by the IP core and increases the maximum operating frequency by 54%,performs better.
Keywords/Search Tags:FIR filter, Distributed algorithm, FPGA
PDF Full Text Request
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