Design And Implementation Of FIR Filter Based On

With the advent of information age and the digital era, digital signal processing has become an extremely important subject and technology. Digital technology revolution led to the birth of a large number of new products and solutions. Along with the revolution is the research and development of digital filters in the field of digital signal processing (DSP). Starting in the1970s, the engineers began to construct special digital filters with discrete component.As the development of FPGA technology, FPGA could be used to design traditional digital logic, digital signal processing and embedded systems. This makes the digital signal processing technology development in the direction of the diversified realization.This paper mainly introduces FIR filter design and the implementation of FIR filter based on FPGA. Based on the parallel distributed algorithm (DA algorithm) a dual channel straight coefficient FIR digital filter with257coefficients is introduced. We add in the general structure of DA LUT, registers, and adders and we give each vector distribution a separate ROM. Then we get a pipelining parallel structure which can be fater. We also introduce FIR digital filters with diffent numbers of coefficients and channels. Test results show that the design in this paper is faster than serial architectures by34%by the cost of20%more Slices and33%more LUTs. The design with independent multipliers has42.7%more Slices and11.8%less LUTs, which is faster than our design by130%. Although the structures that include independent multipliers are more faster, this architecture cost more multipliers which are more less than LUTs and Slices which will introduce more difficulty in large digital design. For example, for Xilinx Virtex-4chip, there are only48independent multipliers in this chip which could not satisfy large scale IC design for filters implemented using multiplier structure. Therefore, our design could balance the needs of rate of fir filters and resources of FPGAs.This article compares filters with different algorithms, framework, numbers of channels and so on. We verify that the sampling rate of filter is lower when the number of channels is larger. For example, the design with1channel and65taps is50%faster than the design with two channels and65taps.