SiPM Reaaout Chip Design

The particle detector is an important device for the frontier research of particle physics and nuclear physics.The "National Major Scientific Research Instrument Development Project" HIRFL-CSR External Target Experiment(CEE),which was approved in 2019,includes T0 detectors,time projection chambers,time-of-flight detectors,and calorimeters distinguish time.In order to reduce the systematic error of the final physical conclusion of the external target experiment,it is necessary to upgrade and add new sub-detectors,and the zero-angle calorimeter is one of them.The calorimeter is in a position that is perpendicular to the center of the collision,and requires a fast and accurate response to measure the time information,energy information and position information of the particles.As the core detector device of the calorimeter,compared with the traditional photomultiplier tube(PMT),the silicon photomultiplier tube(SiPM)has the advantages of high gain,high detection efficiency,low operating voltage and insensitivity to magnetic fields.It will be widely used in the field of particle detection.This subject researches zero-angle calorimeter in the HIRFL-CSR external experiment,and uses SiPM as the detection device in the zero-angle calorimeter.The readout circuit needs to distinguish the particle's hit time information and energy information at the same time.According to the fact that event rate of the external target experiment is 1MHz,and the output signal pulse of the SiPM device is narrow,the response speed is fast,and the time resolution is high,the SiPM readout circuit is designed as follows:1.Each channel adopts the traditional two-branch measurement structure,that is,the two branches collect time information and energy information separately after SiPM photoelectric conversion.The chip integrates a total of 8 channels,the output of energy information is an analog signal,and the output of time information is a digital signal.The specific features are:analog output channel setting gear selection to ensure a good linearity between input and output and more accurate energy measurement information;The time measurement channel judges whether there is a particle hit through the screening circuit,and the counter-type time-to-digital converter calculates the measured time information at the moment of particle hit.In order to reduce the external IO interface,a serial readout method is adopted.The post-simulation results show that the single channel power consumption of the chip is 3.18m W,the area is 1865um x 1970um,the input dynamic range is 10uA-3mA,the accuracy error of the time measurement path is less than 1LSB(25ns),and the output linearity of each gear in the energy measurement path is good.2.With the rapid development of TOT(Time Over Threshold)technology,in response to the traditional structural circuit complexity,low system integration and other shortcomings,a time-to-digital converter(TDC)is used to measure the pulse width of the SiPM output signal,and at the same time obtain the input signal time and energy information.In order to obtain more accurate pulse width information,a high-speed and high-bandwidth comparator is needed in the front end,so the designed for the second chip is an ultra-high-speed comparator.The chip has a fully digital output,in which a constant common-mode circuit improves the stability of the cascaded limiting amplifier;the equalization stage circuit is designed to increase the bandwidth and reduce the "time walk" error;different gain circuits design to obtain a larger input signal dynamic range;rapid discrimination circuit to achieve full-amplitude digital signal output;RSDS interface design not only reduces power consumption but also enhances the driving capability.The post-simulation results show that the single-channel power consumption of the chip is 4.89mW,the chip area is 1065um x 960um,the input dynamic range of the chip is 10uA-4mA,the leading edge timing time walk is about 160ps,and the input and output linearity is good.3.In response to the requirements for the TDC circuit in the first two chips,a two-step TDC circuit based on the counting clock is designed.The method of combining coarse counting and fine counting to achieve high time resolution and large dynamic range.The high precision delay unit is adjusted by the external adjustable voltage to realize the delay adjustment,which is able to offset the random change of the delay unit delay caused by external factors such as PVT.The resolution of the TDC is determined by the delay time of the high-precision delay unit,the clock frequency and the number of bits of the counter determine the dynamic range of the TDC.The post-simulation results show that the TDC can have a resolution of up to 70ps,a dynamic range of 640ns,an RMS of about 3ps,a power consumption of about 1.36mW,and the area is 300um x 40um.Currently,the first two chips have been successfully taped out.The traditional structure chip has been tested.The test results show that the working frequency of the counter in the chip can reach 200MHz,the working frequency of the shift register can reach 100MHz,the time measurement error is less than 1LSB(25ns)under normal working conditions,and the dynamic range is 25ns-6.375us,to meet the design index requirements.In the next step,the second chip will be tested,and the two-step TDC circuit based on the counting clock will be integrated into the two chips to make its performance more perfect.