Quantitative SoC Automated Verification System Based On HVP And Coverage

With the sharp increase in the scale and complexity of modern SoC design,the requirements for verification are getting higher and higher.How to verify the completeness of the verification objectively during the verification process,and quantitatively evaluate the verification quality,so as to achieve a high level of SoC level verification is very challenging.At the same time,how to improve the efficiency of verification,simplify the verification process,and increase the automation of the entire process is also very important to shorten the entire development cycle and effectively reduce project research and development expenditures.In functional verification,coverage is a key criterion for quantitatively evaluating the completeness of verification,but in SoC system-level verification,to save recompilation time,most test cases are written directly in C / C ++,C / C ++ does not directly support functional coverage,which makes it difficult to quantitatively evaluate functional coverage and assertion coverage at the SoC level.Existing SoC-level verification uses the pass rate of test cases to evaluate the verification progress,which makes the probability of defect escape greater,and is extremely unsafe for verification.Therefore,bringing functional coverage and assertion coverage to system-level verification is extremely important.This thesis proposes an automated quantitative verification system.First,model the functional coverage and implement the System Verilog-level coverage task.Use the direct programming interface to import the System Verilog task into the C / C ++ environment to achieve functional coverage at the SoC level.At the same time,summarize common assertions and encapsulate them into task to form an assertion library that can cover daily verification requirements.Also,use direct programming interfaces to introduce assertion task into C / C ++ test cases,realizing the unification of the usage method of functional coverage and assertion coverage at the system level.After that,extract the relevant parameters of the function and the assertion coverage task and add them to the HVP to implement the HVP template with the functional coverage and the assertion coverage,so that the verifier can fill in the functional coverage and assertion coverage related information.Then,use HVP to directly generate functional and assertion coverage related test cases.On this basis,create an automation system to basically automate the above-mentioned workflow.Utilize Python and Makefile to realize the automation of updating HVP template,the automation of test case generation and the automation of mapping.Utilize automation tools to simplify the process.This thesis use functional coverage combined with assertion coverage to achieve quantitative evaluation of verification quality at the system level.At the same time,in the entire process,a verification plan is created starting from HVP,and the final results are all back-marked to HVP.The verification function points,test cases and coverage are all mapped to the original HVP,providing a quantitative evaluation standard for verification.On this basis,the automation system improves the degree of automation of the process and reduces the burden on the verification staff.The automated quantitative verification system designed in this paper is applied to actual verification projects.The application results show that the system achieves automated quantitatively evaluate the quality of verification at the system level.Compared with traditional verification systems,this system reduces the background knowledge requirements for coverage-related verification,automates 80% of the processes,and at the same time improves the vertical and horizontal reuse among projects,which helps improve verification engineers daily work efficiency.