Based On The Eos-chip Mac Module Eda Verification

With the development of information technology and IC technology,IC manufacturing becomes a pillar industry.Consumption demand for integrated circuits is growing rapidly.Up to 50% of the overall development effort is spent on functional and timing verification.Ensuring product quality, reducing development cycles and enhancing have become great challenges for the industry.Therefore, the IC verification has become one of the fastest growing areas in recent years and new tools, technologies and methodologies are rapidly emerging.In this thesis, a thorough investigation into the key technologies in IC verification has been conducted.Based on these technologies, verification of a MAC is performed.The main tasks include constraction of an automated verification platform and fuctional verification, Static timing Analysis(STA) and Formal verification.This thesis surveys the fundamental theories of coverage-driven verification, constrained-random testing, Verification Methodology Manual(VMM), Assertion-based verification, Static Timing Analysis and Formal verification. Based on the analysis of the advantages and disadvantages of traditional verification methods, a new theory named "comprehensive functional verification" is proposed.Experiments shows that it possesses the advantages of guaranteeing adequacy and completeness of verification, shortening the development time, reduceing the cost and enhancing the work efficiency.In this thesis, verificaton is performed on the MAC of an EOS chip.The theory proposed in this thesis can be extended to verify other chips.