Design And FPGA Implementation Of True Random Number Generator Based On Ring Oscillator

With the continuous evolution and upgrade of big data and cloud computing technologies,the risks of data security are becoming increasingly prominent,and information security protection is urgent.Random numbers play a vital role in information security,and they can be used to generate initialization vectors of cryptographic primitives and protocol,encryption algorithm keys,pseudo-random number generator seeds,challenge/response challenge values,and nonce values And system parameters in the safety protocol.A true random number generator is a physical device capable of generating independent and unbiased binary sequences(that is,true random numbers).With the increasing research in the field of reconfigurable computing,this makes field programmable logic gate arrays(FPGA)with extremely high flexibility become the preferred platform for encryption implementation.The thesis focuses on the research of true random number generator based on ring oscillator and FPGA implementation.The main research contents are as follows:(1)Analyzed the clock jitter in the ring oscillator and its sampling principle,studied the effect of inverter delay on the ring oscillator period,and concluded that the non-deterministic local Gaussian jitter in clock jitter is the randomness source of true random number generator based on ring oscillator.(2)Aiming at the entropy source of true random number generator,entropy source structure,and preprocessing scheme based on ring oscillator is designed.The scheme's entropy source structure consists of four inverter chains of different lengths that are mutually prime to form a ring oscillator.The source of randomness comes from the clock jitter accumulated by the ring oscillator inside the FPGA.And after pre-processing by XOR operation,the D-type trigger is used to perform entropy extraction and sampling to output the original random sequence.By analyzing the ent-entropy value of the original random sequence generated by the true random number generator,the structure of the entropy source is obviously superior to the inverter chains of the same length.At the same time,it is proved that the XOR operation can reduce the autocorrelation coefficient of the random sequence and improve the randomness of the sequence.(3)A post-processing method suitable for the structure of the entropy source is designed.To further reduce and eliminate the offset and correlation in the original random sequence,the traditional von Neumann checker is improved.The original random sequence is post-processed by von Neumann checker,thirteen-level XOR chain,m-sequence generator and other secondary modules to realize the output of true random number sequence to ensure that the data compression ratio of the true random number sequence does not change before and after post-processing.After a comparative analysis,it is found that the random number sequence improved by the post-processing module is significantly better than the original random sequence in performance.(4)The proposed true random number generator is implemented on the FPGA development board,which verifies the feasibility of the dissertation design scheme.Use Verilog HDL language to describe and implement the functions of each module of the true random number generator on the FPGA development board.The generated true random number sequence has excellent statistical characteristics and it can pass all test items of the NIST SP800-22 standard statistical package.It meets the quality and security requirements of the encryption module for random number sequences.The designed true random number generator has a high output rate of up to 4Mbps,and the auto-correlation of the generated random number sequence is close to the ideal level,and it can be used in encryption systems and cryptographic chips.