Research On Design Technology Of True Random Number Generator And Physical Unclonable Function Based On FPGA

With the popularity of computer network,Internet of things and portable communication equipment,today's society is in the edge of information explosion.Due to the complex and diverse communication environment,information security has been widely concerned.True random number generator(TRNG)and physical unclonable function(PUF)are basic security primitives,which widely exist in digital signature,certificate generation and chip authentication,and be used as public keys,initialization vectors,and filling values are crucial to security.Field programmable gate array(FPGA),as the carrier of integrated cryptography primitives,algorithms and protocols,is the main platform for TRNG and PUF research.The existing designs based on ring oscillator(RO),phase locked loop(PLL)and delay lock loop(DLL),as the randomness of the output relies on circuit delay high symmetry,require the use of tedious manual wiring and routing,which lead poor portability of TRNG among different devices.In addition,aging effects such as negative bias temperature instability(NBTI),hot carrier injection(HCI),oxide breakdown and electrical migration will lead to the performance and reliability degradation of PUF,which makes the ciphers no longer have high security.In view of the above research problems,this master's thesis carries out research from the following aspects:1.The oscillation modes of RO loop and STR loop are analyzed,and the delay characteristics of oscillation loops in different regions and the essential reasons for the delay differences are studied.2.This dissertation studies the reasons that affect the jitter sampling coverage,and solves the problems of portability and offset of TRNG based on STR ring;A TRNG design based on jitter-latch structure is proposed.The randomness of the output of the structure is improved by increasing the sampling coverage of dither.A special postprocessing circuit is designed to filter most of the deviations introduced in automatic routing,which improves the portability of the design.3.The reason of unstable output of RO PUF was studied;The mixed entropy separation circuit based on PUF is designed.The unstable location in RO PUF is filtered by throughput screening unit to improve the output stability of RO PUF.A multi-layer post-processing structure is designed to output the unstable location as a true random number.4.Having verified two structures,the experimental results show that TRNG based on jitter latch structure can improve the portability of TRNG while ensuring the quality and throughput of random number.The proposed structure has passed all NIST tests with an average p-value of 0.6285 and an average pass rate of 99%,and the output throughput of random number reaches 100Mbps;The scalable hybrid entropy separation circuit based on PUF effectively solves the stability problem of PUF.The stability of PUF is improved by 92.7% compared with that before treatment;The processed random number has passed the randomness test,and the minimum entropy is stable above 0.8.