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Design Of IP Core Of True Random Number Based On PLL

Posted on:2014-07-03Degree:MasterType:Thesis
Country:ChinaCandidate:W X JiangFull Text:PDF
GTID:2268330422967162Subject:Computer application technology
Abstract/Summary:PDF Full Text Request
Random number sequence has been widely applied in science research and engineeringtechnology, it’s increasingly important. Field programmable gate array technology forintegrated on-chip provided conditions for random number generator. The true randomnumber generator is mostly based on the external physical random source, this kind of truerandom number generator has the shortcoming of low speed and poor randomness. Somescholars proposed the design strategy of mixing random number generator, has improvedthe randomness of sequence produced, but without improving its producing efficiency.This paper designs a true random number generator (PLL-TRNG) based on phaselocked loop (PLL), it realize by the IP core, and it improves sequence generating efficiencyand system safety, in premise of generating the sequence’s randomness.This paper analyses the general methods and characteristics of random numbergenerated, on the basis of a commonly used physical random source--the ring oscillator(RO),it compared the characteristics and performance differences between phase-lockedloop and the oscillation ring as random source to generate random sequence; analysis theperformance of the two kinds of truly random number generator at the different samplingfrequency; Do post-processing to the random sequences generated, and eliminate thedeviation of random sequence; and do statistic test and analysis. The test shows that, whenthe sampling frequency is less than1MHz or higher than50MHz, PLL has betterperformance than the RO method to generating random number.PLL-TRNG reaches the target, without affecting the statistical characteristics ofrandom sequence, greatly enhancing the rate of random sequence’s generation, has a goodapplication value.
Keywords/Search Tags:random number generator, field programmable gate array, phase locked loop(PLL), ring oscillator, IP core
PDF Full Text Request
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