Font Size: a A A

Research On Construction And Decoding Implementation Of Spatially Coupled LDPC Codes

Posted on:2021-05-08Degree:MasterType:Thesis
Country:ChinaCandidate:X F WuFull Text:PDF
GTID:2518306107484944Subject:Information and Communication Engineering
Abstract/Summary:PDF Full Text Request
Low Density Parity Check(LDPC)code is a good code that close to the Shannon limit.The sparseness of the check matrix makes it less complex to implement hardware encoding and decoding.Spatially Coupled LDPC(SC-LDPC)codes are a kind of LDPC codes with a special structure.SC-LDPC codes not only have the sparse characteristics of LDPC codes,but also have the association constraint characteristics of convolutional codes.This makes SCLDPC codes has excellent decoding performance under the BEC channel.SC-LDPC codes have received extensive attention and research from related scholars,and have rich application value in various communication scenarios,such as mobile disk storage,relay communication,digital video broadcast communication,and mobile communication.The thesis focuses on the construction method and decoding algorithm of SC-LDPC codes,and propose a codeword construction method with excellent resistance to burst erasure errors.At the same time,a low-latency decoding scheme is proposed.Finally,the improved structure The SC-LDPC code decoder hardware scheme is designed and realized.The main research contents are as follows:(1)This dissertation studies the construction of SC-LDPC code and the sliding window decoding algorithm of SC-LDPC code,introduces the conventional decoding algorithm and analyzes the sliding window decoding algorithm.(2)To solve the problem of SC-LDPC code construction in burst erasure channel,a split asymmetric(SA)structure of SC-LDPC code construction is proposed.Based on the general asymmetric structure,the designed codeword structure divides SC-LDPC code coupling chain into equal length segments,and then splits the coupling elements in the segments into diagonal bands.SA structure can support the sliding window decoding with low complexity and low delay,and improve the burst erasure resistance of the code word.For SA structure,three specific implementation forms are given.Through density evolution,it is theoretically proved that SC-LDPC code of SA structure has better burst erasure performance than that of general asymmetric structure.Performance simulation results show that SA architecture can effectively improve the burst erasure performance of SC-LDPC code.(3)In order to solve the problem of the long decoding delay for the Spatially-Coupled Low-Density Parity-Check(SC-LDPC)code,a Layered Sliding Window Decoding(LSWD)algorithm is proposed.By exploring the quasi-cyclic characteristics of the SC-LDPC subcodeblock and the hierarchical structure of the check matrix in the sliding window,the part of check matrix in the sliding window is layered to optimize the message transfer between two neighbor layers,with the aim of accelerating the convergence of the iterative procedure and reducing the number of decoding iterations.Simulation and analysis results show that the number of iterations in the proposed LSWD algorithm is less than that in the SWD,under the same Signal-to-Noise Ratio(SNR)and the bit error ratio,hence the global decoding delay of the former is effectively shorten.In addition,the decoding performance of the LSWD algorithm was better than the SWD algorithm under the same number of decoding iterations,and the overall computational complexity was slightly increased(4)A hardware decoder based on LSWD algorithm is designed for SC-LDPC code with split asymmetric structure.At the same time,the detailed design of function modules such as cyclic shift,check node update,variable node update and data storage are given.The results of hardware test and software simulation show that the SC-LDPC code layered decoder designed in this dissertation has excellent decoding performance and high decoding data throughput.
Keywords/Search Tags:SC-LDPC, Anti-burst Erase, Protograph Structure, Layered Siding Window Decoding, FPGA Implementation
PDF Full Text Request
Related items