The Research Of Hardware Test Platform For Protograph LDPC Codes Based On FPGA

With the rapid development of information and large demand of multimedia, the transmission reliability of information become more and more important. As the core technology of physical layer in digital communication system, the most important role of channel error correcting code is to ensure the reliability of information transmission. Compared with traditional wide range of mobile communication, some of the lower BER requirement of specific applications, such as: magnetic recording system, high-definition digital TV system, the wireless medical human network, etc, it is particularly important to the reliability of information transmission. These applications typically require the BER of10-10, we call it a very-low error rate, and excellent channel error correcting code can provide such a extremely low BER performance. Low density parity check (LDPC) code is one of the best kinds of such codes, it is a block code with very excellent performance. Protograh-LDPC codes is one kind of low density parity check code, compare with the traditional LDPC codes, it has a simpler structure and is easier to extend and hardware implementation. It also has a very excellent performance and meet the requirement of very low bit error rate in some communication systems.In usually studies, people’s attention is focused on how to construct better code and find better encoding and decoding algorithms, they are less concern about how to verify that the code is a good code and to evaluate the complexity of the application. Performance validation can be divided into theoretical validation and experimental simulation test. It lack of reliable analysis methods of mathematical for randomly construct LDPC codes, so the experimental simulation test become the most important method of performace validation in such applications. As the method based on Field-Programmable Gate Array(FPGA) hardware emulation platform, because of their fast spped and reconfigurable characteristics, it became a very effective verification method of channel error correct coedes, particularly for such applications with requirement of very low bit error rate.For this reason, this paper mainly studies the design of Protograph-LDPC code test platform based on FPGA, such platform with reconfiguration is for the study of different Protograh-LDPC codes at extremely low bit error rate. The major work of this paper is as flollows:1. We improved the traditional extend method of Protograph-LDPC code, used looping structure to extend the Protograh-LDPC code. It can maintain the excellent performance and also reduces the complexity of hardware implementation for applying this improved method.2. We designed a hardware test platform of Protograph LDPC code applied in AWGN channel. We divided the whole system to some submodules and designed every submodule independently. At last, we tested a kind of Protograph LDPC code in this platform and the BER can reach10-11～10-12.3. For further research, we also designed a hardware test platform of Protograph LDPC code applied in magnetic recording channel. We used the EPR4model as the magnetic recording channel.At last, the BER of the selected Protograph LDPC code can reach10-9～10-10by using this hardware platform.