Design And Implementation Of A Burst Communication System Based On FPGA

With the development of communication technology,how to suppress the interference effectively is one of the main problems in the military communication system.Burst communication,as a short-term,high-speed,random transmission of data anti-jamming technology has been widely used in military communications systems.Based on the research project "xxxx system",the system can send and receive information data in a very short period of time.In this paper,a data frame structure of burst communication system is designed,and the key technology of the system is to be the GMSK which has the constant envelope and smoothing phase,and LDPC which has the superior performance.Based on the principle and simulation results of GMSK and LDPC,the burst communication system is implemented in FPGA.And the paper gives the realization process,simulation data waveform and test results.The main work of this paper is as follows:1.Based on the system parameter,a data frame structure is proposed in which the synchronization sequence and the information sequence are interspersed with each other,and a synchronization scheme combining symbol synchronization and frame synchronization is designed.The synchronization scheme is used to realize the timing synchronization and synchronization acquisition of the burst communication system,so that the receiving end can accurately recover the information data and improve the reliability of the system.2.According to the theoretical analysis and performance comparison of GMSK modulation and demodulation scheme,the data frame is modulated by using the waveform storage quadrature modulation scheme at the transmitting end,and the data in the look-up table is stored by the ROM to reduce the logic resources in the FPGA.At the receiving end,the GMSK signal is decomposed by Laurent,and the differential coherent demodulation scheme is used to demodulate.This way can make full use of the storage resources of FPGA to complete synchronization,rotation and judgment.3.According to the principle of LDPC coding and decoding scheme and the difficulty of FPGA implementation,the quasi-cyclic coding scheme is used at the transmitting end to utilize the characteristics of its shift register and the abundant logic resources of FPGA to realize the LDPC coding process.At the receiving end,UMP BP-Based algorithm which can greatly reduce the logic computation of FPGA is used as the LDPC decoding scheme.4.Based on burst communication system hardware platform,we can download the FPGA program and test it.The test results show that the burst communication system can transmit and receive data correctly in a short time,and the quality of the transmitting signal is good,and the frame error rate of the system satisfies the parameter requirements.