Design And Verification Of A Digital HD Video Interface

With the continuous development of multimedia neighborhoods,people's requirements for image clarity continue to increase.High-definition digital video interface technology has gradually developed and matured,with special design standards and development directions.At present,new digital video interface standards such as DVI,HDMI and Display Port seem to be more able to meet the needs of the market.According to the specifications of DVI 1.0,this thesis designed a high-end digital video interface transmitting end,combined with receiving end to carry out all-round verification,and completed the design of the entire system.According to the protocol requirements,the thesis completes the design work of system coding and phase-locked loop modeling,analyzes the design from the system level and the module level,and verifies the system from the module level to the system level.The design was improved and improved based on feedback from performance analysis and verification.The final goal of the thesis was achieved-the design of the DVI video interface sender(to enable it to be correctly encoded and finally transmitted in binary form).The DVI transmitting end includes: an input-output port,an encoding circuit,a phase-locked loop circuit,and a serial-to-parallel conversion circuit.The input and output ports are responsible for collecting and outputting data,which is mainly composed of a logic circuit composed of an ESD circuit and a power pull-down circuit and an input port;the encoding circuit is mainly composed of a digital logic circuit that encodes according to a protocol;the phase-locked loop circuit is the solution of the entire system clock Circuit;Parallel-to-serial conversion circuit realizes the conversion of10-bit parallel data to 10-bit serial data.According to the TMDS protocol,the encoding at the sending end is completed.According to the requirements of the entire sending end,a clock circuit-phase-locked loop was designed,and according to the characteristics of this project,the modules of the phase-locked loop were optimized.Finally,through text analysis of the verification results,the final results show that this design meets the requirements of the project,and the video can be transmitted correctly.This article completes the TMDS encoding,realizes the conversion of 8-bit parallel input data to 10-bit parallel data,and then realizes the output of 10-bit serialized data through a parallel-to-serial conversion circuit.Through the traversal of the 8-bit input data(256 sets of data),plus the already-accepted receiving end to verify the correctness of the entire encoding,the results show that the encoding is correct.Based on the analysis of the overall structure of the phase-locked loop,a phase-locked loop is designed.The output frequency of the phase-locked loop is 250 MHz ? 1.65 GHz,and the highest transmission rate can reach 1.65 Gb / S.When the input clock is 25 MHz,the peak-to-peak noise jitter is 0.51%.When the input clock is 1.65 GHz,the peak-to-peak noise jitter is 0.46%,Which meets the system's requirement that the input noise is less than 2.5%.