Design And Optimization Of AES Encryption And Decryption Based On SOPC

Generally,most of the encryption algorithm can be implemented with software,but also can be based on hardware.The software encryption does not cost much and is easy to achieve,implement simple and convenient.But software encryption is limited to the software platform,it is easy to be attacked by hackers.The hardware encryption security is much higher than the software encryption,and its encryption speed is generally faster than the software encryption.At the same time,it can be meet the requirements of real-time and can be applied to many occasions.At present,AES algorithm has become the mainstream of hardware encryption,so it is more and more important to implement AES encryption algorithm in a fast and secure way.SOPC technology is the use of programmable logic chip Altera company,which can be a system on a chip with fast speed,portability,anti-interference and so on.Most SOPC development software with a rich IP core library support for developers,who can also design specific IP core with hardware description language flexibly,according to the specific application.Combined with the practice of the internship company,this paper designs a AES encryption and decryption system based on SOPC,and optimized the AES algorithm to improve its security and speed of operation.The main content are as follows:Primarily,Make a further research on AES encryption algorithm and SOPC technology.Through the research background of AES encryption algorithm and the development status of SOPC technology,we know that the AES encryption algorithm have the characteristics of safety and reliability,and fast speed of encryption and decryption.Owing to the characteristics of flexible design,portability,low development cost,short development cycle of SOPC technology,the AES encryption algorithm was implemented in the SOPC system.Afterwards,optimizing AES algorithm.The S-Box used in the process of AES encryption has a disadvantage of iteration cycle.A new S-Box created in the design.The construction of S-Box requires two steps of inverse multiplication and affine transformation.It shows that the iteration cycle is related to the affine transformation.The iteration cycle respond to changes with affine transformation,which can be 256 at the most.Meanwhile,the Mix-Column module was also optimized by decomposing addition and multiplication.The optimized operation was suitable for the operation of the hardware circuit to achieve.The security and speed of AES were improved obviously.In the part of hardware implementation,this paper designed an optimized IP AES kernel by compiling Vreilog hardware description language.By using Quartus II,SOPC Builder software and DE2-70 development board,a new small AES encryption and decryption system were constructed with the new AES IP core,Nios II processor and some necessary peripherals reasonable matched.In the Nios II IDE software to complete the system encryption test by using C language,to achieve human-computer interaction operation.The design results were simulated by Modelsim software,and the correctness of the encryption results was verified.The final test and simulation results showed that the design used less on-chip hardware resources,to achieve a fast and efficient AES encryption and decryption.In the next step,it will move this design to the company's products,which applied to the encryption and decryption of personal information.