SOPC-based Digital Video Interface Technology Developed

SOPC technology has the characteristics of hardware and software co-design, which makes the system hardware development fast and efficient and brings lots of convenience for the hardware upgrades in future. In this way, the system development cycle is shortened, the system cost is saved, and the system life cycle is extended. Use of FPGA hardware-based rapid, parallel processing features, enables system data processing and transmission rate greatly improved. Performance in the data buffer and compression is stable and fast, and the system is small in size and at low power.Using SOPC technology and appropriate image compression algorithm, the subject structures the system in which a single FPGA as the main carrier embedded by a NiosⅡcore, and can transmits video data via the Ethernet digital display interface. Meanwhile, by decoding by the DVI digital video signals for image shrinking ping-pong frame buffer, compression, DMA transfer to the Ethernet controller, the video signals transmitted using twisted-pair is verified.SOPC-based digital video interface dedicates to the DVI data transmission, which mainly includes a front-end DVI receiver module, a data sample and buffer module, a data compression module, a NiosⅡ-embedded control system and an Ethernet control circuit. Two of them, the data compression module and the NiosⅡ-embedded control system, are built into the single FPGA, which comes to a SOC. the NiosⅡ-embedded control system integrates a NiosⅡcore, a DMA controller, an Ethernet controller interface, some programmable I/O and a three-state Bridge components, while the two data buffer RAM are constructed by a built-in.The key performance of the system is the bandwidth. Decoding speed Of the DVI receiving, the data compression speed and compression ratio, the transfer rate of DMA and Ethernet, will all affect the bandwidth of the system. So the system design pays attention to the matching rate among various modules, and make NiosⅡprocessor control each module's run together.Technical characteristics of the system:the compression and transfer used in Ping-pong mode, Compressed data are transferred to the Ethernet controller by the DMA of the NiosⅡsystem.This use the mature Ethernet controller port components of NiosⅡsystem and ensure the high-speed of data transmission. In addition, the main components of the system are in single chip FPGA, which not only makes the system smaller, but also is more convenient and flexible in upgrade and modification.