Simulation And Analysis Of SoC High-speed Memory System Performance Based On SystemC

With the advancement of processing technology,due to the difference in processing speed between CPUs and different access modes,DDR usually does not reach the theoretical bandwidth in actual So C,and allows multiple master devices to access DDR in parallel,resulting in So C performance.Demand is getting higher and higher,and storage systems are the main limiting factor for performance gains.The traditional model focuses on the interaction between the controller and the DRAM.This study builds a full-system simulation that captures the interaction between the memory system and the rest of the So C.Although the RTL design method is accurate,the modeling process is complex and the simulation speed is slow.If the design definition of the architecture design phase cannot meet the requirements of system function,performance and cost during the RTL design and verification phase,it will lead to a lot of repetitive work.Therefore,it is becoming more and more important to perform system-level performance simulation and optimization in chip architecture design.It is necessary to establish a front-end model that reflects the target design requirements in order to adjust the So C's IP configuration to optimize system performance.The System C language supports system-level modeling and simulation of software and hardware collaboration,and the models it describes can be validated before the system is implemented.The scripting language only needs the corresponding interpreter as the running mode without compiling,and the simulation speed block can be used to automate the simulation process,which can effectively improve the chip development efficiency and increase the controllability.The main research methods used in this thesis are model method and experimental method,which study the high demand of DDR performance of complex system baseband chips.Based on System C,the performance simulation model for So C memory system is abstracted.First,the System C model of the DMA as a traffic injector is defined,and the simulation input file is generated by analyzing the traffic of the system-level use case.Combined with the System C model of the LPDDR4 controller,the adapter integrates with the No C's System C model into a complete System C simulation environment.Based on the simulation environment,define the automation simulation and post-processing script to automate the simulation process.By continuously simulating iterations and analysis,exploring the configuration space,optimizing the data transfer efficiency and accessperformance between other components and DDR,selecting a set of configuration parameters that best suit the project requirements,avoiding further changes in low-level implementation and verification.Commissioning takes more time.Its application can be extended to other system-on-chip,and performance simulation is not limited to the memory system.Transaction-level design and simulation work in the architecture design phase can be realized by certain configuration changes and instantiations.The System C simulation platform established in this thesis can effectively evaluate the performance of So C high-speed memory system.Firstly,the test case simulation is used to analyze the bandwidth resources and delays occupied by different initiators and different behaviors in the shared DDR.Secondly,the parameters that measure the efficiency of DDR memory access are defined,and the evaluation criteria of efficiency are summarized.The main factors affecting DDR utilization can be explored from two aspects.One is from the working principle of DDR: longer burst brings more efficiency;mixed read/write commands provide more scheduling options.On the other hand,through a large number of simulation analysis and changing different system parameters,we can find out the factors affecting the memory performance in the So C system.First adjust the FIFO size,which can increase the throughput by 8% compared to the default configuration,reducing the read latency by 6% to 10%.Secondly,the distance of the bank conflict is increased in the command queue.It is seen from the simulation results that the read delay is greatly reduced,and the change in throughput is not obvious.Creating a large write burst adds 254.2MB/s(11%)of space.For pre-charge and activation experience costs,DPU increased by 449MB/s(28%),average read latency increased by 2-6%,and write throughput increased by 1-3%.