A Design On High Performance DSP Memory Controller

The processor-memory speed gap is increasing with the rapid development of the micro processor design and manufacture technique. The speed of processor is increased about 60% a year but the main memory access speed is increased only about 10% a year. The performance of the memory system becomes the bottle-neck of the DSP systems. Proper memory controller design becomes the critical performance factor of DSP system.In this thesis, we process an extensive research on general used high performance DSP architecture. And then present the research on how to design and implement the on-chip memory controller based on ADI TS201.Our design of memory controller includes the cache module, DRAM module, state register module, LRU (Least resent used) replacement arithmetic module, clock divide module and cross bar module. The cache module is the most complicated one, and it contains the read buffer, the write back buffer and the cache.We aimed at the behavior of the memory controller when a bus access asserted to progress the optimization. We replaced the LRU replacement arithmetic to the PLRU replacement arithmetic. And alter the serial judgment of the cache/buffer to parallel. We also carried out the function validation and timing validation to guarantee that our design could work correctly.At last, we draw the conclusion that the optimization could improve the performance of the design for about 10% under the smic180nm library.