Performance Analysis Of Off-Chip Memory Architecture

Memory access performance is the major bottleneck of the performance of modern computer system. Over the past twenty years, advances in process technology and circuit design have produced an annual increase in processor speed of 60%, whereas DRAM speed has only increased at an annual rate of approximately 10%. The memory gap causes dozens of cycles, even hundreds of cycles stall, when a cache miss occurs. It greatly decreases the performance of entire system. Thus, how to improve memory access performance has been an important direction in computer architecture research. The performance of memory system embodies in two aspects: latency and bandwidth. Off-chip memory latency is mainly determined by DRAM latency, and memory bandwidth is determined by data transfer rate through the memory bus.The basic DRAM cell is comprised of a transistor and a capacitor. The digit that is saved in the storage cell is determined as logic 1 or 0, by the voltage potential stored inside the capacitor. Before accessing the bit cell, the bit lines need to be precharged to 1/2VCC. Precharging operation is the most fundamental step for all the commands or operations of the DRAM. Therefore, a complete DRAM access composes three portions: row activating, column access, and precharge.Modern DRAMs support two page strategies: close page and open page. In close page strategy, DRAM latency composes row activating latency and column access latency. The close page strategy allows the precharge to begin immediately after current access. In open page strategy, if the next access to the same bank goes to the same page(page hit), only column access is necessary. However, if the next access is a page miss, additional precharge cycle is needed. Which strategy will win mainly depends on the access patterns of applications. Modern DRAMs also support multi-bank interleaving. Page strategy and bank interleave make space of improving the performance of DRAM system.This dissertation mainly focuses on the performance of off-chip memory system. It introduces how to model SDRAM controller in C language, analyzes the impact of open page and bank interleave, and evaluates the effect of page hit and bank interleave by different address mapping manner. In order to find out the behavior of applications when a page miss occurs, we analyze the memory access mode of SPEC CPU2000 programs from the point view of the length of consecutive page-hit access, average page interval for the recent 32...