Performance Analysis And Research Of DDR Controller Based On AXI Bus

With the rapid development of modern integrated circuits,So C technology has become a common method in the field of chip design.In an So C system,the gap between the processor and the memory is growing,and the memory access efficiency has determined the performance of the entire So C system.The most important part of memory access is the design of the memory controller.Therefore,it is very important to study the optimization design of the storage controller to improve the performance of the entire system.At the same time,in the face of more application requirements and highly integrated So C design,the current transmission performance of the chip can only be evaluated by the subsequent design of the actual measurement of the sample,which will greatly increase the overall chip design cost and verification cycle.Therefore,the RTL-level internal module performance analysis research is currently a reliable and effective solution.Based on the in-depth analysis of the characteristics of DDR memory and the highbandwidth AXI bus,this thesis carried out the optimization design and performance monitoring and verification platform for the prototype DDR memory controller.First,after carefully analyzing the basic structure of the prototype storage controller,combined with the problems sorted out,a three-point optimization design is proposed,and at the same time,the actual performance requirements are targeted for monitoring and analysis of the chip's transmission performance.Finally,the performance monitoring environment is used to perform detailed performance analysis and quantification of the controller before and after optimization.Therefore,the main research work of the thesis includes the following aspects:1.Carefully study the structural characteristics of the prototype controller and put forward three optimizations: 1)port arbitration design for multi-transaction multi-channel;2)pre-access XOR mapping design for early basic mapping;3)multi-command Memory access arbitration reordering memory access scheduling design.Targeted optimization effectively improves data bandwidth utilization and reduces memory access latency.2.Designed the AXI bus performance monitor using System Verilog language,supporting the printing and text output of the main bus performance indicators,and at the same time,using python scripts to divide the performance indicators in the output text into steps to complete the RTL level transmission performance image Real-time output waveform.3.Build a universal UVM verification environment,design the verification environment components,and finally bind the performance design module to the UVM verification environment of the DDR controller,so as to complete the function verification and performance testing and monitor the performance indicators.The thesis conducted a comprehensive test for the above optimized design combined with the performance verification environment.First,a comprehensive functional verification of the optimized controller function was performed to ensure the effectiveness of the entire optimized design.At the same time,this article conducted a detailed performance comparison analysis on the optimized address mapping,the optimized memory access strategy,and the multi-transaction big data transmission before and after optimization.The final result shows that the optimization of address mapping can improve data transmission by 12% to 14% Utilization,read and write latency can be reduced by about 20%;memory access scheduling optimization can improve throughput by about 26%,memory access latency can be reduced by about 20%;controller latency can be increased by 16%? 45 %.The host throughput is increased by about 70% compared to the prototype controller,and the effective bandwidth of the storage system can be increased to about 1.9GB/s.