Research On DSP Module Verification In DTV Tuning Chip

At present,the design of communication chip faces two challenges: one is the increasing design complexity,the other is the urgent project cycle.This also brings a severe challenges to the work of communication chip verification.The verification method combining direct verification and FPGA verification is often adopted by many communication IC design companies.However,the verification completeness and efficiency of direct verification are low,while the FPGA verification has some defects such as difficult to locate errors and too long synthesis time.Therefore,how to improve the efficiency and completeness of communication chip verification,quickly locate and solve errors in the simulation phase,and reduce the workload of FPGA verification in the later stage has become an urgent problem to be solved.In this thesis,a verification method suitable for complex communication algorithm module is proposed,which takes the digital signal processing(DSP)module in DTV tuning chip as a verification object.An algorithm equivalence verification platform is desigend for the function points of DSP module,and a UVM verification platform for non-algorithm function points.The combination of the two verification platforms can achieve the complete function verification of DSP module.The structure of the DSP module and the functions of the internal sub-modules is analyzed firstly.And then,the algorithm equivalence verification requirements of the DSP module is put forward according to the characteristics of its converted from algorithm model.Based on System Verilog language,the algorithm equivalence verification platform is built,and standard components such as driver,scoreboard and interface are designed.In addition,special components such as wrapper module,register configuration module,and simulation signal generation module are designed for the algorithm equivalence verification to meet the verification requirements.At the same time,considering the differences between RTL design and algorithm model,UVM is proposed to verify non-algorithm function points,and UVM verification platform is applied to the verification of multiple function points to improve the varification efficiency.After the design of the two verification platforms is completed,the design unter test is simulated and verified.Finally,the code coverage and function coverage are collected and analyzed.All test cases of the DSP module passed,and the line coverage was around 90%.The uncovered code is analyzed and 100% coverage is achieved in the module-level traversal verification,and the functional coverage reached 100%.Compared with the traditional UVM verification,the verification method proposed in this thesis uses the existing MATLAB algorithm model to verify the algorithm equivalence,eliminating the time for the verifier to learn communication knowledge and implement the reference model by themselves.For non-algorithmic function points,UVM verification is carried out,retaining its advantages of standardization and reusability.The combination of the two verification methods quickly found multiple bugs during the progress of the project,so that the subsequent FPGA boardlevel verification did not have obvious vulnerabilities,greatly accelerated the verification process,and finally successfully taped out and mass produced.