Behavior Model Design For Signal Monitoring Comparator Module Based On Verilog-AMS

With the increasing complexity of integrated circuit, digital and analog mixed signal systems are becoming more and more popular. At verification process for mixed system design, using spice simulation method in all verification stage will significantly extend the period to verify and sbw down the speed of iterative design, but using the digital discrete function model will lose the simulation accuracy and performance parameters. Based on mature mixed signal modeling method, the thesis analyses and models the signal monitoring comparator to make tradeoff between the precision and speed of simulation and meet the mixed signal verification requirements and needs.This thesis mainly studies high level behavioral model of signal monitoring comparator circuit based on the Verilog-AMS language. The thesis firstry introduces application background of this circuit and characteristics of the Verilog-AMS platform, and then introduces the working principles and main structure of the DAC and comparator, and selects the circuit structure modelled in paper through these introductions and analyses of these circuit structures. Finalry, the comparator circuit is divided to several independent circuit modules with different functions and circuit structures, through the theoretical analyses of behavior characteristics of these modules, these behavior models are established by using the Verilog-AMS language, at the same time these models are simulated by Cadence emulational tools.The results of the simulation show the open loop gain of comparator model is 80dB, compared with Spice simulation the error is 1.25%, under low and high speed mode setup time respectivery 38.8ns and 2.2 us, compared with Spice simulation the error are within 20%; DAC setup times are respectivery 79ns and 63ns in 3V and 1.5V reference source, working current is 9.1μA, compared with spice simulation setup times error are within 20%, the current error is 3.3%; total system operating current is 21 μA, compared with spice simulation the error is 10%. Compare and analyze these simulation waveforms with these real circuit waveforms, it shows that the behavioral modeling can not only reflect the real physical characteristics of the circuit in a certain extent and ensure the emulational accuracy by using Verilog-AMS language to model digital and analog mixed signal system, it also can promote the emulational time more than 50 times to speed up the design and verification. The research work of this paper not only shows effectiveness and feasibility to use these models to replace the related real circuits in design and verification processes.