Verification Of New Functions Of USB4 Based On UVM

In recent years,the size of integrated circuits is gradually shrinking,which is accompanied by higher design complexity and greater difficulty in verification.To meet the function verification during chip development,more efficient verification methods are needed.Circuit design efficiency plays a crucial role.More and more USB-based electronic products have appeared in daily life.In order to adapt to the rapid development of large-scale storage,the USB organization has continuously updated its interface protocol.At present,the data transmission speed of USB has been increased to 40 Gb / S.The latest version of USB4 already supports a variety of data and display protocols,and can simultaneously carry three types of data transmission: USB3,DP,and PCIe,and dynamically share the bandwidth of USB4.The improvement of the performance of USB4 has higher requirements for the protection of SOC chip functions,so the verification of USB4 IP seems very necessary.This topic originates from a company project,aiming to achieve a standardized,reusable USB4 IP verification platform based on UVM verification methodology,and strictly analyze and verify the integrity and reliability of the design function under test to ensure The functional coverage and code coverage of the design meet the project requirements,thereby achieving a complete USB4 IP verification.The verification work of the USB4 project is carried out by setting up a verification environment.First,the USB4 protocol is studied,including the functions of the protocol adapter layer,configuration layer,transmission layer,logic layer,and electrical layer specified in the protocol.Extract function verification points and develop a verification plan based on the USB4 system architecture.According to the verification plan,this paper builds a USB4 system verification environment based on UVM.In order to improve the reusability of the environment,this project introduces UVC components.Through its configuration and connection,communication between the design under test and the verification environment can be achieved.Test incentives drive the design under test.Test incentives are written based on the functional verification points,and the USB4 system-level functional verification is simulated.Generate a coverage report based on the simulation results,adjust and add new test cases to make the coverage meet the project requirements.This project finally realized the design of the USB4 system verification environment,which is based on UVM and has high reusability.According to the verification plan,USB4 function points are verified through test cases,which ensures that the quality of the design under test of USB4 meets expectations.This topic can provide valuable reference for related research on USB4 verification direction.