Symmetry Algorithm CE Module Verification Based On UVM

With the increasing complexity of SoC design,it is particularly important to protect the information security of SOC chip.CE module with symmetrical algorithm(AES,DES,TDES)has been integrated into SOC chip system frequently.With the increase of the scale and complexity of chip design,the input of verification work is also increasing.Verification plays a very important role in the chip production.A good verification method and environment can improve the efficiency and reusability of verification.With the development of verification industry,UVM methodology with many advantages has become the main verification method.UVM methodology can not only improve the efficiency of verification,but also has high reusability for later verifiers.Based on UVM methodology and system Verilog language,this paper builds a high reliability verification platform for CE module of symmetric algorithm,and then writes test cases to simulate the actual scene,and verifies the function of CE module through dynamic simulation.In-depth study of CE module design principles,as well as the relationship and interaction between the various modules,according to the requirements of the design,put forward the function to be verified.Then,according to the interaction between the modules and the function points that need to be verified,the overall framework of the verification platform is designed,and the construction and connection of each component are carried out in the whole framework environment.In this verification platform design,it is divided into the following aspects to ensure the reliability of the platform.First,through the analysis of the function points,the corresponding test incentives are constructed,and then the incentives are sent to the DUT through the driver component.Secondly,through the research and analysis of the principles of the operation modes(CBC,EBC,CTR,OFB,CFB,GCM,CBC_MAC)of the algorithm,C language is used to construct C model,which is compared with the output of DUT as the expected model to ensure the correctness of encryption and decryption data.On the output interface of DUT,a monitor component can be constructed to detect the behavior and output data of DUT.The data on the output interface is sent to the scoreboard through the function of conversion class and conversion function,as well as the connection of port.In the scoreboard,the comparer function in UVM methodology is used to realize automatic comparison.Finally,the coverage model is constructed and a large number of regression tests are carried out to collect the coverage.Analyze the places that are not covered,modify the test cases to simulate the directional excitation,so that the functional coverage reaches 100%.At the same time of collecting function coverage,we use simulation tools to collect code coverage and analyze the code that is not covered.If the code that is not covered is explained,the code that can be covered will be modified and the test case will continue to be covered.After the completion of the verification platform the EDA tools such as VCs and Verdi are used for simulation and analysis.At the end of the paper,the simulation results and coverage rate are presented.In the coverage rate results,the function coverage rate reaches 100%,and the code coverage rate reaches 96.62%.The expected goal has been achieved.At the same time,it also proves that the verification platform designed in this paper has completed the functional verification of CE module reliably.