Research And Design Of Fully Differential Fourth-Order Delta-Sigma Modulator

With the continuous development of information technology,the demand for high-performance Delta-Sigma ADC is increasing day by day.Because discrete-time Delta-Sigma ADCs are more insensitive to clocks and processes,they have high application and research value.The discrete-time Delta-Sigma ADC system is composed of a modulator and a down-sampling filter.The down-sampling filter is a digital filter,and the core analog circuits of the ADC are located in the modulator.Therefore,this paper has designed a Delta-Sigma modulator applied to instrumentation.The main work of the thesis includes: Based on the in-depth study of oversampling and noise shaping techniques,several common structures of Delta-Sigma modulators are compared and analyzed.At the system design level,based on the discrete-time architecture,a single-loop feed-forward 4-order 4-bit quantization design scheme is proposed.Firstly,the system parameters are designed.In order to achieve good system stability,the calculation is performed by setting the pole z = 0.91 of the noise transfer function as the boundary condition,and verified by the ideal Simulink model.Secondly,considering the actual circuit application,various non-ideal factors need to be verified.For each non-ideal factor,the model is separately modeled and compared with the ideal model to complete the quantitative evaluation,which provides a basis for circuit-level optimization design.Finally,the DWA algorithm is modeled and verified,and the improvement of the effective number of bits and circuit harmonics when the system is corrected by the DWA algorithm is simulated.The simulation results show that the effective number of bits in the model after DWA correction is significantly improved.So for high performance modulator system design,DWA correction is necessary and effective.At the circuit design level,this article designs and simulates the quantizer,feedback DAC,integrator,clock generation circuit,and feedforward summation adder based on the modular design.Among them,the quantizer uses a Flash ADC with a dominant speed,and focuses on the design of the comparator circuit.The quantization speed is optimized to make the error smaller.The system offset is 217 V and the random error is 1.67 m V.The feedback DAC uses a thermometer code instead of the traditional binary control to achieve a smaller DAC nonlinearity.The integrator adopts a SC integrator with delay,which focuses on the design of the op amp circuit,and the circuit structure with gain-improving stage realizes a high gain of 122 dB.The clock circuit outputs a non-overlapping clock with a 45% duty cycle accurately at the input of 1MHz.The feedforward summation adder uses an active adder,the performance is more advantageous than the passive type.The simulation results for the overall circuit of the modulator show that under the sine wave condition of input amplitude 0.7V and frequency 1.77 kHz,the effective number of bits of the modulator at OSR 32 can reach 14.85 bits and the SNDR can reach 91.16 dB.When the input frequency is lower(305Hz),the circuit can achieve a better result of 15.23 bits and SNDR 93.4dB.