Design Of Fourth-order Sigma Delta ADC With Feedforward

The rapid development of very large scale integrated circuit makes theanalog-to-digital converter to obtain the considerable development. Due to the low cost,high resolution, the requirement of anti aliasing filter is low, the tolerance of matchingaccuracy is high, Sigma-Delta ADC is widely used in audio signal processing andinertial device. MEMS center is developing micro accelerometer inertial device, ofwhich the frequency of signal processed is low and the accuracy requirements isrelatively high. This paper designs a Sigma-Delta ADCapplied in the interface circuit ofinertial device, including four order feed-forward modulator and decimation filter,simulated with0.6μm process.This paper designs a four-order modulator with feedforward sum structure toreduce the output levels of each integrator,1-bit quantization structure to reduce thenonlinear quantization, coefficient optimization is also adopted to reduce powerconsumption, achieving a high signal-to-noise ratio. The signal bandwidth is500Hz andthe sampling clock frequency is256kHz. At first, the behavioral modulator model isbuilt by MATLAB Simulink and SD Toolbox, getting signal-to-noise ratio100.5dB,effective number of bits16.4, then the circuit level design is processed in the Cadenceenvironment using switched capacitor circuit, dynamic comparator is adopted toimprove speedand reduce power consumption, a fully differential operational amplifieris designed to lessen inhibition of even harmonics, the two-phase non overlapping clockis designed to reduce the channel charge injection effect.The simulation of circuit-levelmodulator is done in0.6μm process,getting the signal-to-noise ratio94.7dB andeffective number of bits15.44.The decimation filter is also designed in this paper.At first, the working principleof decimation filter is analyzed, which is realized by CIC filter, half band filter and halfband filter, forming a three cascade structure. The filter finallyachieve128times downsampling and reconstructs the original input signal from1-bit digital signal, removingthe out of band noise. Secondly, behavior level design is done in MATLAB andtheRTLlevel design is done using Modelsim. Finally, the DC synthesize of the decimationfilter is done and the layout of it is given with Encounter.