Research And Design Of ESD For Memory Interface

With the development of semiconductor technology processes,the gate oxygen thickness is getting thinner and more fragile in the chip.At the same time,with the development of highspeed and high-frequency circuits,the contradiction between smaller parasitic capacitances and higher robustness of ESD protection is growing.There is also an irreconcilable contradiction between ESD robustness and smaller chip areas.In this context,ESD protection of the chip becomes particularly important.The basic theory of ESD protection is explained in this paper,including commonly used ESD models and test standards,the principles of commonly used ESD devices,design of guard rings in ESD,ESD failure analysis,and the whole process of ESD work in engineering.N + / PWell diodes,P + / NWell diodes and GGNMOS are deeply researched.The influence of several parameters on the robustness and parasitic capacitance of the device is analyzed,and the theoretical analysis results of the parameters such as robustness,turn-on voltage and secondary breakdown voltage are verified by TLP test.At the same time,the theoretical analysis of the failure in N + / PWell diodes during the test is carried out.The analysis results are verified by TLP test,and an effective solution is given.The circuit structure and working principles of the existing ESD power-rail clamp circuit are analyzed and studied.For the contradiction between its area and the discharge time and the poor ability to prevent false triggering,two improved circuits are proposed.A prolonged discharge time power-rail clamp circuit with two RC paths,and a power-rail clamp circuit against false trigger with Transient and Static Hybrid-Triggered,respectively.Cadence Spectre is used to simulate and verify the circuits.The results show that the discharge time of the power-rail clamp circuit with prolonged discharge time reaches 1.45 times that of the traditional circuit,the area is reduced to 79%,and the false trigger current is also reduced by two orders of magnitude.The false trigger current of the power clamp circuit anti-false trigger is reduced by 4 orders of magnitude,and the area is only 71% of the traditional circuit.The structural characteristics of the input and output PAD in high-speed I / O interface and their protection emphasis of ESD circuit are analyzed.Aiming at the special requirements of the high-speed memory bidirectional interface of DQ in 800 Mbps?1600 Mbps DDR3 SDRAM with a 65 nm CMOS technology,the ESD protection structure design based on power-rail is carried out,including the ESD design of both interface and power-rail clamp circuit.ESD layout design,full chip ESD plane layout are accomplished.Full chip test results show that the design can withstand 3000 V HBM and 200 V CDM electrostatic pulses,meeting the design specifications.