Fault Detection And Redundancy Design For Interconnection In 3D-IC

As semiconductor technology continues to scale,interconnect delay and power consumption threaten to limit the benefits of further scaling.To overcome these bottlenecks,the semiconductor industry is exploring 3D integration e.g.,through die stacking and through-silicon-vias(TSVs).However,due to limitations of the manufacturing process level in chip production,there will be some failure TSV which will lead to the failure of the entire chip.Therefore the detection of TSV failure is important way to improve the yield of three-dimensional chips.This paper will propose modeling,testing and repair methods of TSV failure.The main work are listed as follows.(1)Based on TSV technology and manufacturing structures,the electrical equivalent model of TSV is established.The electrical effects of different TSV fault is obtained by HSPICE simulation.The variation of TSV-tosubstrate resistance caused by TSV defects can be mapped to the change of path delay so that the related fault can be detected.(2)A Celluar-Automation-based fault detection architecture is proposed for bonding wire in interposer.Due to the characteristics of single attractor in cellular automata,it is possible to detect a row of interconnection in parallel quickly.And the detection structure is also suitable for a large number of TSVs.(3)We propose a TSV redundancy structure based on cellular network.Every redundant array is a dual fault-tolerant bi-directional redundant structure.The cellular-network structure not only ensures a high repair rate but also reduces the routing circuit cos.When the total number of TSVs is 1000,0.2% of the redundancy rate can reach 99.9980% repair rate.