Research And Design Based On Enhancing Scan Chain Security Of Cipher Chips

With the rapid development of digital information,the design scale of integrated circuits is gradually increasing,making testability technology more critical.The design-for-test(DFT)structure based on scan chain is widely used in manufacturing test,which can directly access the deeply embedded logic part to improve the test quality of the circuit,is also used by attackers to retrieve the password information stored on the chip at the same time.In recent years,an article has proposed a highly threatening ScanSAT attack technology,which is based on Boolean satisfiability attacks and combined with the testability function of scan chains to attack existing defense designs.In recent years,it's a highly threatening ScanSAT attack technology that has been proposed in the article,which is based on Boolean satisfiability(SAT)attacks and combined with the testability function of the scan chain to attack existing defense designs.In order to resist this attack method,research work based on the security of scan chain is carried out in this paper.Various security scanning methods have been proposed to deal with the contradiction between testability and security brought about by testability technology.One of the security scan chain structure is to confirm the user's identity through the key,and the other is to improve the security scan structure of the circuit through logic obfuscation,which obfuscates the scan data by randomly adding logic gates to the scan chain structure to limit the controllability and observability of the trigger.A dynamic key security scan chain circuit that increases the security of the scan chain structure based on the protection method of the scan chain structure is proposed in this paper to to resist the more threatening ScanSAT attack.It can effectively resist various threats from scan chain attacks without reducing circuit performance and testability.Only when the input data is valid or authorized test stimulus,the correct data in the scan chain can be removed by the user,and then the valid test stimulus is moved to the scan chain and applied on the circuit in the proposed security scan chain structure.Security keys that are different from each other are used for different test stimuli.The key is to design a generator circuit that can dynamically generates the key,avoiding the key data of the static storage and the circuit in operation.There is also a pseudo-response generator in the design to generate pseudo-response data corresponding to incorrect excitation.When the original test stimulus specifies valid key data,the matching seed data is calculated by the design to construct a specific test stimulus,so that the attacker cannot convert the test stimulus to extract the correct response from the scan chain or retrieve the key from registers.So the design has a very high level of security and its security will not be reduced no matter how many guesses the attacker tries because of the dynamic nature.Finally,the AES cryptographic circuit is used as the reference circuit,and the scan chain and the dynamic key security scan circuit are inserted into the reference circuit.Then the logic synthesis and specific vector test of the overall circuit are carried out and the validation test is completed.finally the safety and testability of the overall circuit are analyzed.The results show that the security of the dynamic key security scan chain structure can reach the order of 1.72*1028 when the key bit width is 9,and the additional area overhead increases by 0.17%.The fault coverage rate is 100%based on stuck-at,and there is no effect on the performance of the original circuit.This structure,which is accompanied by good practicability and high security level,can effectively resist almost all existing scan chain attacks without affecting circuit testability and test coverage.