Design And Implementation Of Interface Conversion Module Based On Gigabit Ethernet

In the process of aircraft development,a data recording device is required to collect and save important information of the aircraft during the test process,which is convenient for later analysis of the aircraft’s working conditions during the test period,and provides data support for the next test and technical improvement.With the rapid development of bus communication technology and chip technology,the research on high-speed communication of data recording devices has gradually become a hot spot.Because of its simple structure,easy implementation and strong compatibility,the Gigabit Ethernet interface circuit is widely used in high-speed data transmission.In this paper,an interface conversion module is designed based on Gigabit Ethernet.As part of the data recording device,the main work of this module is as follows:1.Design the implementation scheme of Gigabit Ethernet: design the Ethernet interface circuit in the way of "FPGA+PHY chip",and carry out Gigabit Ethernet communication through the UDP/IP protocol to achieve high-speed data transmission;for the packet loss existing in the UDP protocol To solve the problem,design the instruction confirmation mechanism and the request retransmission mechanism to ensure the reliability of both instructions and data during Ethernet communication.2.Design the hardware interface circuit: through the synchronous 422 circuit,the LVDS interface circuit performs data transmission with other modules,and re-frames the received data of different types into the memory through the method of mixed framing to improve the interface conversion module compatibility.3.Design the FPGA online update function: In view of the limitations of the traditional JTAG update method,the FPGA has the characteristics of multiple configurations,and the configuration file is stored in the Flash through the Ethernet interface to realize the online update of the FPGA and reduce the difficulty and environmental requirements of the later program update.4.Build a test platform.According to the designed system test process,read the memory data several times in succession,each time reading 4GB of data,and analyze the data integrity through the data analysis of the host computer and the Wire Shake packet capture software.The entire Ethernet communication process is stable and reliable,and there is no data loss;at the same time,the Bandwidth Meter Pro software is used to monitor the Ethernet transmission rate in real time,showing that the average rate of the Ethernet is actually about 29.3MBps.The FPGA online update is carried out under normal and sudden power failure,respectively.After the end,the host computer can work normally,and the FPGA configuration is successful.