Design And Research On Compatible Interface Of 10 Gigabit Network Synthetic Test System

The device must have ability to deal with large amounts of data for each functional module, and the network bandwidth should reach 10 G level. At the same time, the development of science and technology provides a variety of options for aviation electronic systems with high speed data communication, including 10 Gigabit Ethernet and fiber channel technology for COTS network technology, which all can be used as support and supplement of the avionics bus technology. The 10 Gigabit network test system can test and debug network performance of avionics system, which can be seen below.The design of compatible interface aims to achieve physically interface-compatible result between 10 Gigabit Ethernet and Fiber Channel network. In this dissertation, two network physical layer specification standards are analyzed and compared, which illustrates that the compatible interface design is feasible. The function modules of compatible interface include hardware interface circuit module and the hardware logical function module,the hardware interface circuit can support data transmission of 1/10 GE and 1/2/4/8GFC. Basic performance and application characteristics of X2 and SFP+ are compared, and SFP+ optical device is selected. There are two advantages of SFP+, which is compliance with universal design requirement. A clock data restorer of single-channel and four-channel is selected based on compatible design requirements. This paper has completed a schematic diagram of hardware interface circuit and a PCB design.The compatible interface logic function module includes physical layer data processing module, XGMII improvement interface, clock management unit and data management unit. Physical layer data processing module has improved GTX IPCore, and use its Ser Des module, which mainly realizes the basic logical function of the interface compatibility. Improved XGMII interface can support different data transfer rate of Ethernet and Fibre Channel. The clock management units is responsible for clock synchronization of network communication, and provides the system reference clock signal. The data management unit is responsible for configure the control signal.This paper has verified the function of compatible interface,including functional simulation by Modelsim and functional test in the development board.The improvedGTX in the development board can support different speed networks.The simulation of logic function module includes serial-parallel conversion module, codec module, FC FSM module, CRC module, scrambling and descrambling module, XGMII improvement interface, and 10 G MAC module. The functional verification of compatible modules has proved the correctness of the compatible design. The physical integration of the two networks is basically achieved by means of network interface compatible designs.