Parallel Readout Method Based On Gigabit Ethernet For Physical Experiments

With the development of the detector technology, new detectors with higher precision, smaller granularity and larger extent have been developed and applied, which lead to a sharp increase of data rate. At the same time, because of the complexity of the background particles in heavy substance research experiments, data selection in software method has taken the place of the traditional way of hardware selection and it also led to the increase of data rate. Therefore, how to transfer tremendous amounts of data from the FEE (Front-End-Electronics) to the DAQ becomes a critical issue.This thesis analyzes the data transmission methods in physical experiments and proposes a transmission scheme based on Gigabit Ethernet for the CBM-973 project. The main purpose is to solve the high speed and high density data readout for the research&test of the MRPC (Multi-gap timing Resistive-Plate Counter) and the FPGA TDC for the CBM-TOF. The essential idea of this scheme is to reduce the complexity of the data readout topology and to use the standard communication protocol as close to the FEE as possible. Taking this method can not only improve the performance of the data throughput, but also simplify the system structure of both the hardware and the software.A prototype system based on PXI chassis is proposed under the guidance of this parallel readout architecture, aiming at research&test of the CBM-TOF MRPC and FPGA TDC. This scheme is based on the rich experience in the readout technology of physical experiment at present. The PXI chassis offers the system configuration, trigger and timing, and mechanical and power supplies. Parallel readout is implemented by the ROB (Read-Out-Board) module.The research and design of the ROB module is the central part of this thesis. The ROB module is implemented by state-of-the-art SoC FPGA technology which packages FPGA and ARM processor in a single die. The thesis focuses on three points. Firstly, the design of FEE interface is studied. Secondly, the high speed and high efficiency data transfer method from FPGA portion to HPS portion (including hardware and software designs) under SoC FPGA architecture is studied. Finally, the realization of high efficiency TCP data transfer at user space is proposed. By adding the reliable transfer function to the SPI-4.2 (System Packet Interface Level 4 Phase 2) protocol, the proposed RSPI (Reliable SPI-4.2) protocol can transfer data unidirectionally with reliable property. This is a big advantage for FEE, as the main data stream direction for FEE is upward. By implementing a cycle buffer of DMA descriptors in the FPGA portion, a high efficiency transfer method from the FPGA portion to the HPS portion is implemented. This method has advantages of high transfer speed, low CPU load and low interrupt frequency. The test shows that the method can offer nearly 754MBytes/s (6.032Gbps) transfer speed with only 21% total CPU load. The frontend subsystem of BESIII DAQ is used as the main reference for the DAQ interface implementation. The state machine based state management and synchronization method is used to make sure that all the ROBs run in coherent state. For the data transfer method with TCP protocol, both standard read/send and splice system calls are implemented and compared. The splice call is introduced to Linux mainly for zero copied data transimission between file descriptors, i.e. file to socket. Depending on the EMAC (Ethernet Media Access Control) features, the splice system call introduces at most one copy for file to socket transmission. Finally, the integration of processor into FPGA makes ROB very reconfigurable.Based on the above discussion, a low profile (L8cm*W5cm*H1.2cm) ROB hardware is implemented and corresponding test in laboratory environment is processed. Test results indicate transmission speed under full link reaches 58MBytes/s (464Mbps), meanwhile the CPU usage is only 64%.Because of its flexibility, ROB can not only be used in physical experiments, but also be used in other areas such as intelligent instruments, Internet of Things and monitoring.