| Waiting time jitter in time division multiplexed digital communication systems occurs when several lower rate digital signals are multiplexed to a higher data rate using pulse stuffing.;An experimental desynchronizer for a standard M12 multiplex system has been built. The peak-to-peak and the rms jitter of the recovered clock have been measured, and the jitter spectrum has been obtained. A peak-to-peak waiting time jitter of less than 0.2 unit intervals (UI), with an rms jitter value of less than 0.03 UI has been achieved over most of the DS-1 frequency range. Results show that the waiting time jitter is reduced, as compared to the presently-used clock recovery method, by a factor of about 2. (Abstract shortened by UMI.).;A new approach is described for reducing the waiting time jitter. An improved desynchronizer is proposed, which makes use of the information (normally discarded) contained in the irregular stuff bit pattern. The new clock recovery circuit, named a differential PLL (DPLL), operates at the low frequency stuffing rate, so that very tight control of the recovered clock frequency can be obtained. Therefore, the waiting time jitter on the recovered digital signal can be reduced. |
