A delta sigma based buck converter-analysis and design

This work describes how a delta sigma (DeltaSigma) based DC-DC step down converter (buck converter) can be chosen for powering wireless applications. Wireless systems require that their power supplies have low noise in addition to being compact. They also require that these power supplies do not drain the battery quickly thereby reducing the battery life. Low drop out regulators (LDO) are traditionally used because of their excellent noise performance and simple compact architecture. However, the power efficiency of LDOs declines as the difference between the input and output voltages increases and therefore reduces the effective life of the battery. The standard switching buck regulators using Pulse Width Modulation (PWM) controllers on the other hand, offer higher efficiency and therefore can achieve better battery performance but have large spurs at integer multiples of the clock frequency.;In this work, a buck regulator that has a delta sigma (DeltaSigma) controller is analyzed as an alternative to provide both good power efficiency and better spurious performance for low noise. While previous work have shown the feasibility of replacing the DeltaSigma controller with the DE controller, this work provides a step-by-step methodology for designing the DeltaSigma buck regulator for wireless applications. It first analyzes the impact of the various design parameters of the DeltaSigma controller such as order, over sampling ratio (OSR) and input voltage (Vin) on its spurious performance and efficiency. The spurious requirements of various wireless standards such as WIFI, Bluetooth, GSM and W-CDMA, HSPA, LTE and WIMAX are then explored. Out of these standards, the GSM system was found to have the most stringent spurious performance requirement and as a result was used as the default standard in this work. The tradeoffs in selecting the different design parameters for a fixed Vin are then investigated for GSM system.;Using the values for order and OSR, the optimal DeltaSigma modulator parameters are theoretically established. Then, using these parameters, the DeltaSigma buck regulator is designed with 0.5microm CMOS technology and simulated for key parameters such as spurious performance, efficiency and transient response and compared against the standard requirements of a buck converter thereby establishing a design methodology. It is shown that a 3rd order DeltaSigma controller with OSR of 32 can meet the stringent spectral requirements of a GSM system by a 10dB margin with 8% better power efficiency compared to the PWM controller. In addition to the spurious and efficiency performances, this thesis also analyzes the impact of static and dynamic load changes on this DeltaSigma buck regulator. It is shown that for a 13% change in output voltage VOUT, the DeltaSigma buck regulator can still meet the spurious constraints of the GSM system.